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Gyuris, US

Jeno Gyuris, Lincoln, MA US

Patent application numberDescriptionPublished
20080234304N3-Pyridyl-Thiamine And Its Use In Cancer Treatments - The invention provides methods using N3-pyridyl-thiamine compounds and pharmaceutical compositions comprising N3-pyridyl-thiamine, which are especially useful for preventing or reducing tumor growth in vivo. The invention is also directed to the benefits of reducing thiamine concentrations, e.g., by means of a thiamine reduced diet, as an effective step in a therapeutic regime for patients treated with N3-pyridyl-thiamine.09-25-2008
20100003258FIBROBLAST GROWTH FACTOR RECEPTOR 3 (FGFR3) BINDING PROTEINS - Monoclonal antibodies that bind and inhibit activation of fibroblast growth factor receptor 3 (FGFR3) are disclosed. The antibodies can be used to treat cell proliferative diseases and disorders, including certain forms of cancer, associated with activation of FGFR3.01-07-2010
20100173361Hepatocyte Growth Factor (HGF) Binding Proteins - The present invention provides a family of binding proteins that bind and neutralize the activity of hepatocyte growth factor (HGF), in particular human HGF. The binding proteins can be used as diagnostic and/or therapeutic agents. With regard to their therapeutic activity, the binding proteins can be used to treat certain HGF responsive disorders, for example, certain HGF responsive tumors.07-08-2010
20100173362Hepatocyte Growth Factor (HGF) Binding Proteins - The present invention provides a family of binding proteins that bind and neutralize the activity of hepatocyte growth factor (HGF), in particular human HGF. The binding proteins can be used as diagnostic and/or therapeutic agents. With regard to their therapeutic activity, the binding proteins can be used to treat certain HGF responsive disorders, for example, certain HGF responsive tumors.07-08-2010

Viktor Gyuris, Wappingers Falls, NY US

Patent application numberDescriptionPublished
20080243462INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR - A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.10-02-2008
20080270748HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A PARALLEL STRUCTURE OF USER MODELS TO SUPPORT A LARGER USER MODEL SIZE - A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.10-30-2008

Patent applications by Viktor Gyuris, Wappingers Falls, NY US

Viktor S. Gyuris, Newton Center, MA US

Patent application numberDescriptionPublished
20110078388FACILITATING MEMORY ACCESSES - In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.03-31-2011

Viktor S. Gyuris, Wappingers Falls, NY US

Patent application numberDescriptionPublished
20080215830EMPLOYING A DATA STRUCTURE OF READILY ACCESSIBLE UNITS OF MEMORY TO FACILITATE MEMORY ACCESS - A data structure of readily accessible units of memory is provided. The data structure includes designations of one or more units of memory that while represented in the data structure do not need expensive address translation, other tests or special handling in order to access the units of memory. By employing such a data structure, memory access and system performance are enhanced.09-04-2008
20080243468PROVIDING MEMORY CONSISTENCY IN AN EMULATED PROCESSING ENVIRONMENT - Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.10-02-2008
20080244570FACILITATING COMMUNICATION WITHIN AN EMULATED PROCESSING ENVIRONMENT - Communication between processors and I/O communications processes is facilitated. During the communication, shared control blocks and input/output queues are updated without using locks. Instead, a lockless capability is provided to update the queues and control blocks, thereby enhancing system performance and minimizing the need for recovery processes.10-02-2008
20090083720EMPLOYING IDENTIFIERS PROVIDED BY AN OPERATING SYSTEM OF A PROCESSING ENVIRONMENT TO OPTIMIZE THE PROCESSING ENVIRONMENT - Optimizations are provided for processing environments. Selected memory objects are tagged with unique identifiers by an operating system of the environment, and those identifiers are used to manage processing within the environment. By detecting by a processing platform of the environment that a memory object has been tagged with a unique identifier, certain tasks may be bypassed and/or memory objects may be reused, even if located at a different location.03-26-2009