Gyh-Bin
Gyh-Bin Wang, Hsinchu TW
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20090009224 | Multiphase DLL using 3-edge phase detector for wide-range operation - The invention discloses a new architecture of multiphase delay-locked loop (DLL) with innovative 3-edge phase detector (3-edge PD), which compares the VCDL's first delay interval and the last delay interval to send an Up pulse or a Dn pulse to adjust the interval among those delay clock phases. The DLL may achieve both wide-range operation and multiple clock phase generation, and is also immune to multi-selection problem. | 01-08-2009 |
Gyh-Bin Wang, Jhudong Township TW
Patent application number | Description | Published |
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20120229146 | High Speed Test Circuit and Method - A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock. | 09-13-2012 |
Gyh-Bin Wang, Hsinchu County TW
Patent application number | Description | Published |
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20150287445 | METHOD FOR CONTROLLING MEMORY DEVICE ASYNCHRONOUSLY WITH RESPECT TO SYSTEM CLOCK, AND RELATED MEMORY DEVICE AND MEMORY SYSTEM - A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission. | 10-08-2015 |