| Patent application number | Description | Published |
|---|
| 20090103391 | Memory clock generator having multiple clock modes - An integrated circuit | 04-23-2009 |
| 20090129194 | Access collision within a multiport memory - A multiport memory | 05-21-2009 |
| 20100195365 | ROM array - A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design. | 08-05-2010 |
| 20100329044 | Assisting write operations to data storage cells - A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal. | 12-30-2010 |
| 20110072323 | Supporting scan functions within memories - A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch. | 03-24-2011 |
| 20110122712 | Controlling voltage levels applied to access devices when accessing storage cells in a memory - A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line. | 05-26-2011 |
| 20110149674 | Integrated circuit memory with word line driving helper circuits - An integrated circuit memory | 06-23-2011 |
| 20110187438 | Reducing current leakage in a semiconductor device - An integrated circuit, method of controlling power supplied to semiconductor devices, a method of designing an integrated circuit and a computer program product are disclosed. The integrated circuit comprises: a semiconductor device for handling data; a power source for powering said semiconductor device, said power source comprising a high voltage source for supplying a high voltage level and a low voltage source for supplying a low voltage level; a plurality of switching devices arranged between at least one of the high or low voltage sources and the semiconductor device. There is also a control device for controlling a first set of the plurality of switching devices to connect one of the high or low voltage sources to the semiconductor device and for controlling a second set of the plurality of switching devices to connect the one of the high or low voltage sources to the semiconductor device. At least some of the first set of the plurality of switching devices have a higher resistance when closed and providing a connection than at least some of the second set of the plurality of switching devices such that when the first set of the plurality of switching devices connect the semiconductor device to the one of the voltage sources the semiconductor device operates with a lower performance than when the second set of the plurality of switching devices connect the semiconductor device to the one of said voltage sources. | 08-04-2011 |
