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Gurumurthy, AZ
Charan Gurumurthy, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090314519 | Direct layer laser lamination for electrical bump substrates, and processes of making same - A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug. | 12-24-2009 |
| 20100078826 | SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE - An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads. | 04-01-2010 |
| 20110108427 | SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE - An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads. | 05-12-2011 |
Charan K. Gurumurthy, Higley, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080251932 | Method of forming through-silicon vias with stress buffer collars and resulting devices - A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. | 10-16-2008 |
| 20090250824 | METHOD AND APPARATUS TO REDUCE PIN VOIDS - A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder. | 10-08-2009 |
| 20100078805 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 04-01-2010 |
| 20100148365 | GRID ARRAY CONNECTION DEVICE AND METHOD - A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. | 06-17-2010 |
| 20100289154 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 11-18-2010 |
| 20110169167 | GRID ARRAY CONNECTION DEVICE AND METHOD - A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. | 07-14-2011 |
Charavana Gurumurthy, Higley, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090277866 | Method of enabling solder deposition on a substrate and electronic package formed thereby - An electronic package includes a substrate ( | 11-12-2009 |
Charavana K. Gurumurthy, Higley, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 06-23-2011 |
Charavanakumara Gurumurthy, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110147933 | MULTIPLE SURFACE FINISHES FOR MICROELECTRONIC PACKAGE SUBSTRATES - Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask. | 06-23-2011 |
Charavanakumara Gurumurthy, Higley, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20120077054 | ELECTROLYTIC GOLD OR GOLD PALLADIUM SURFACE FINISH APPLICATION IN CORELESS SUBSTRATE PROCESSING - Electronic assemblies including coreless substrates having a surface finish, and their manufacture, are described. One method includes electrolytically plating a first copper layer on a metal core in an opening in a patterned photoresist layer. A gold layer is electrolytically plated on the first copper layer in the opening. An electrolytically plated palladium layer is formed on the gold layer. A second copper layer is electrolytically plated on the palladium layer. After the electrolytically plating the second copper layer, the metal core and the first copper layer are removed, wherein a coreless substrate remains. Other embodiments are described and claimed. | 03-29-2012 |