| Patent application number | Description | Published |
|---|
| 20100052758 | Stage by stage delay current-summing slew rate controller - A stage by stage delay current-summing slew rate controller includes a delay controller, a delay cell array, a current source array, a switch array, a load. The delay cell array includes N delay cells, the switch array includes N switches, and the switch includes N current sources, wherein N>1. The delay controller is connected with the control ports of the delay cells respectively, and the delay cells are connected with the control terminal of the switches respectively. One of the connecting terminals of the switch is connected with the output end of the current source, and the other end of the connecting terminals of the switch is connected with one end of the load, and the other end of the load is connected to the ground. | 03-04-2010 |
| 20100123497 | Phase delay line - A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage equal division to time equal division converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the input of the voltage equal division to time equal division converter. The voltage can be precisely divided, and the number of the phases can be easily controlled and expanded. The band gap reference technology enables the working points not affected by the temperature. The negative feedback mechanism of the phase-locked loop determines the period, phase, duty-cycle of the sawtooth wave are same with the reference clock. The ascending and descending time of the sawtooth wave are precisely equal. | 05-20-2010 |
| 20100315120 | Dynamic adaptive terminal load adjusting method and circuit - A dynamic adaptive terminal load adjustment method includes comparing a voltage on an on-chip termination impedance driven by an on-chip current source with a voltage of a band gap reference circuit to get an optimal trimming parameter by an adaptive control mechanism, wherein the optimal trimming parameter is applied to a terminal by an output control circuit to have a feedback control. The present invention is on-chip so the cost is saved. The terminal is separated from the adjusting circuit, thus the present invention has a good dynamic performance. Compared with laser trimming, no expensive cost is needed in the present invention. The present invention saves an IO pin without an external device, has the good temperature characteristic and high resistance regulation accuracy. Furthermore, the adjusting circuit is separated from the terminal load circuit by high matching of relative resistance of CMOS process, thus reducing the adverse impact. | 12-16-2010 |
| 20100315149 | High-speed data compared latch with auto-adjustment of offset - A high-speed data compared latch with auto-adjustment of offset, includes input pair transistors P, input pair transistors N, a compared latch module, an input control module, an output control module and a offset logic control module, the offset logic control module creates two control signals that regulate the number of input pair transistors P and input pair transistors N respectively according to reset signal RESET and the latched output of the compared latch module, and achieve self correcting of offset through regulating the number of the input pair transistors P and the input pair transistors N. The present invention is a feedback mechanism, automatically trimming the number of differential input pair to achieve the trimming differential pair operating point and the threshold voltage, eliminate the process variation, and latch on more precise control match the differential input pair transistors of the high-speed data compared latch in receiver accurately. | 12-16-2010 |
| 20110025392 | Duty cycle correction method and its implementing circuit - A duty cycle correction method comprises detecting independently a relative delay time of two input differential signals; equating the sum of two relative delay time with the cycle of the input differential signals; and adjusting the two delay time to the same value. A corresponding implementation circuit comprises two time delay units; two correlation phase detectors connecting simultaneously with each of the two time delay units; a charge pump connecting with the output of each of the two correlation phase detectors, with its output connecting to the two time delay units in order to form a loop; and a synthesis output unit connecting with both the time delay units, thereby generating output signals. The adjusting range of duty cycle becomes much wider. The implementation circuit is absolutely symmetrical, so a duty cycle with high accuracy can be obtain. | 02-03-2011 |
| 20110051779 | Spread spectrum clock generating circuit - A spread spectrum generating circuit comprises an external PLL and an internal PLL. The external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively. The frequency divider is connected to the phase detector in order to form an external loop. The internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively. An output terminal of the voltage-controlled oscillator connects with a counter, and the output terminal of the counter connects to an input of the oscillator in order to form an internal loop. The present invention is compatible with the conventional ones, and has lower design risk and higher circuit reliability; compared with the general circuit, it has drastically reduced the area and power consumption, which allows more flexible design and meets more demands. | 03-03-2011 |
