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Guo, Singapore
Bing Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20080233451 | Proton-exchange composite containing nanoparticles having outer oligomeric ionomer, and methods of forming - A proton-exchange composite includes a polymer matrix formed from a proton-exchange polymer and ionomer particles distributed therein. The polymer has side chains with ionic groups. The particles have an average particle size of less than 20 nm and include an oligomeric ionomer that interacts with the polymer and attracts the ionic groups on its side chains. The composite may be formed by a method in which an initiator is bonded to silica particulates. The initiator is used to initiate polymerization of a precursor monomer to form a salt form of the oligomeric ionomer bonded to the silica particulates, which is then reacted with an acid to produce the oligomeric ionomer, thus forming the ionomer particles. The ionomer particles are dispersed in a solution containing a solvent and the polymer dissolved therein. The solvent is removed. The residue is cured to form the composite. | 09-25-2008 |
Chang Ming Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20110136935 | BONE AND/OR DENTAL CEMENT COMPOSITION AND USES THEREOF - The present invention provides a composition comprising: at least one viscosity-enhancing agent; and at least one macromonomer. In particular, the composition may be a bone cement composition and/or a dental cement composition. The composition may be used in medicine. The composition may be used in orthopedic and/or periodontal applications. The present invention also provides uses of the composition. | 06-09-2011 |
Dianbo Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100321100 | NEGATIVE ANALOG SWITCH DESIGN - A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage. | 12-23-2010 |
| 20110057715 | HIGH BANDWIDTH SWITCH DESIGN - An analog switch includes a transistor having a current path between an input and an output, a gate coupled to a control terminal, and a bulk terminal, and a switched bulk control circuit coupled to the control terminal, the bulk terminal, and ground to reduce an equivalent capacitance seen from a source terminal or drain terminal of the transistor towards the bulk terminal of the transistor. The bulk control circuit includes an all-NMOS bulk control circuit if an NMOS transistor switch is used. | 03-10-2011 |
| 20110133810 | System and Method for a Semiconductor Switch - In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node. | 06-09-2011 |
| 20110133813 | ANALOG SWITCH WITH A LOW FLATNESS OPERATING CHARACTERISTIC - An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor. | 06-09-2011 |
| 20110156794 | GATE CONTROL CIRCUIT FOR HIGH BANDWIDTH SWITCH DESIGN - An analog switch configuration includes a gate control circuit coupled between an input of a switch and a gate of the switch. The gate control circuit passes voltage changes on the input of the switch to the gate of the switch to decrease the influence the inherent gate to input capacitance has on the bandwidth of the switch. By reducing the change in voltage across the inherent capacitance, the current through the capacitance in decreased as well as its influence on the bandwidth of the configuration. | 06-30-2011 |
Hongtu Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100189339 | System and method for inspecting a wafer - A method for inspecting a wafer. The method comprises a training process for creating reference images. The training process comprises capturing a number of images of a first wafer of unknown quality, each of the number of images of the first wafer being captured at a predetermined contrast illumination and each of the number of images of the first wafer comprising a plurality of pixels. The training process also comprises determining a plurality of reference intensities for each of the plurality of pixels of each of the number of images of the first wafer, calculating a plurality of statistical parameters for the plurality of reference intensities of each of the plurality of pixels of each of the number of images of the first wafer, and selecting a plurality of reference images from the plurality of images of the first wafer based on the calculated plurality of statistical parameters. The method for inspecting the wafer further comprises capturing an image of a second wafer, the second wafer being of an unknown quality, selecting a first reference image from the plurality of reference images, and comparing the captured image of the second wafer with the first reference image to thereby determine at least one of presence and type of defect on the second wafer. | 07-29-2010 |
Huaqun Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20110047630 | METHOD AND SYSTEM FOR TAMPER PROOFING A SYSTEM OF INTERCONNECTED ELECTRONIC DEVICES - A method and system for tamper proofing a system of interconnected electronic devices. The method comprises splitting embedded software of each electronic device into at least two executable parts, a stationary part residing in memory of said each electronic device and a non-stationary part residing in memory of another electronic device. | 02-24-2011 |
Lihui Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20090128436 | On-chip inductor with trimmable inductance, a method for making the same and a method for adjusting the impedance of the inductance - Means for trimming an inductor on a chip for use in RFID tags. The inductor coil ( | 05-21-2009 |
| 20100055673 | TRANSPARENT MICROFLUIDIC DEVICE - A device for analysing the status of a biological entity. The device ( | 03-04-2010 |
Li Hui Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100025095 | Device Carrying an Intergrated Circuit/Components and Method of Producing the Same - A method of forming an integrated circuit component on an insulating substrate ( | 02-04-2010 |
| 20100052064 | METHOD FOR STRAINING A SEMICONDUCTOR WAFER AND A WAFER SUBSTRATE UNIT USED THEREIN - The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit. | 03-04-2010 |
| 20110036912 | On-Chip Antenna and a Method of Fabricating the Same - An on-chip antenna fabricated on a chip for wireless communication is disclosed. The on-chip antenna includes a first dielectric layer arranged on a surface of the chip of the radio frequency identification tag, a grounded shielding layer arranged on the first dielectric layer, a second dielectric layer arranged on the grounded shielding layer, and a planar antenna arranged on the second dielectric layer above the grounded shielding layer. A radio frequency identification tag with an on-chip antenna and a method of fabricating an on-chip antenna on a chip for wireless communication are also disclosed. | 02-17-2011 |
Qiang Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20090250818 | VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE - An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer. | 10-08-2009 |
Tang He Guo, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20090043923 | Method for data transfer between host and device - The present invention relates to a method for data transfer between a host and a device as well as to respective apparatus. A host is seen as a communication apparatus which organizes data traffic. A device is seen as dependent on the host. In a tiered-star topology there are usually multiple devices connected to one host. | 02-12-2009 |