Patent application number | Description | Published |
20110012629 | REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE - After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state). | 01-20-2011 |
20110042786 | INTEGRATION OF PASSIVE DEVICE STRUCTURES WITH METAL GATE LAYERS - A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions. | 02-24-2011 |
20110049673 | Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design. | 03-03-2011 |
20110083786 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 04-14-2011 |
20110095379 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 04-28-2011 |
20110115022 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers. | 05-19-2011 |
20110115044 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-19-2011 |
20110121370 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material. | 05-26-2011 |
20110127637 | Nanopillar E-Fuse Structure and Process - Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure. | 06-02-2011 |
20110254098 | INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS - A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric. | 10-20-2011 |
20120061772 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 03-15-2012 |
20120112310 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-10-2012 |
20120261728 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. | 10-18-2012 |
20130056802 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of | 03-07-2013 |
20140035068 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 02-06-2014 |
Patent application number | Description | Published |
20110037128 | METHOD AND STRUCTURE FOR IMPROVING UNIFORMITY OF PASSIVE DEVICES IN METAL GATE TECHNOLOGY - Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region. | 02-17-2011 |
20110049624 | MOSFET ON SILICON-ON-INSULATOR REDX WITH ASYMMETRIC SOURCE-DRAIN CONTACTS - A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region. | 03-03-2011 |
20110215300 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 09-08-2011 |
20110215405 | PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES - A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing. | 09-08-2011 |
20110227043 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 09-22-2011 |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 10-06-2011 |
20110248321 | Self-Aligned Contacts for Field Effect Transistor Devices - A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region. | 10-13-2011 |
20110248343 | Schottky FET With All Metal Gate - A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer. | 10-13-2011 |
20110248362 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 10-13-2011 |
20110298060 | INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface. | 12-08-2011 |
20110315961 | Ultrathin Spacer Formation for Carbon-Based FET - A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET. | 12-29-2011 |
20110316565 | SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR - A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule. | 12-29-2011 |
20120007054 | Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity. | 01-12-2012 |
20120007181 | Schottky FET Fabricated With Gate Last Process - A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region. | 01-12-2012 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 01-12-2012 |
20120037991 | Silicon on Insulator Field Effect Device - A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material. | 02-16-2012 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 02-16-2012 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 02-16-2012 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 02-23-2012 |
20120043620 | Multiple Threshold Voltages in Field Effect Transistor Devices - A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device. | 02-23-2012 |
20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-03-2012 |
20120119266 | Stressor in Planar Field Effect Transistor Device - A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region. | 05-17-2012 |
20120139062 | SELF-ALIGNED CONTACT COMBINED WITH A REPLACEMENT METAL GATE/HIGH-K GATE DIELECTRIC - A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer. | 06-07-2012 |
20120146001 | ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET - A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer. | 06-14-2012 |
20120181616 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 07-19-2012 |
20120187375 | Deposition On A Nanowire Using Atomic Layer Deposition - In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire. | 07-26-2012 |
20120193712 | FinFET STRUCTURE HAVING FULLY SILICIDED FIN - A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins. | 08-02-2012 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 11-08-2012 |
20120280322 | Self-Aligned Contacts for Field Effect Transistor Devices - A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w). | 11-08-2012 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 11-15-2012 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 11-15-2012 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 11-22-2012 |
20120292701 | Silicon on Insulator Field Effect Device - A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate, the first silicide material arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material. | 11-22-2012 |
20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 11-22-2012 |
20120299104 | SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS - A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate. | 11-29-2012 |
20120299118 | Multiple Threshold Voltages in Field Effect Transistor Devices - A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel. | 11-29-2012 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 11-29-2012 |
20120312452 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 12-13-2012 |
20120326125 | Deposition On A Nanowire Using Atomic Layer Deposition - A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape. | 12-27-2012 |
20120326236 | MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 12-27-2012 |
20120329193 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-27-2012 |
20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 07-04-2013 |
20130230978 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 09-05-2013 |
20130328016 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-12-2013 |
20140170844 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 06-19-2014 |
20150137078 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 05-21-2015 |
Patent application number | Description | Published |
20120132913 | III-V Compound Semiconductor Material Passivation With Crystalline Interlayer - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 05-31-2012 |
20120187505 | Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 07-26-2012 |
20120220114 | TENSILE STRESS ENHANCEMENT OF NITRIDE FILM FOR STRESSED CHANNEL FIELD EFFECT TRANSISTOR FABRICATION - A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET. | 08-30-2012 |
20120235247 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 09-20-2012 |
20120248509 | STRUCTURE AND PROCESS FOR METAL FILL IN REPLACEMENT METAL GATE INTEGRATION - Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack. | 10-04-2012 |
20120256294 | Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design. | 10-11-2012 |
20120268985 | RESONANCE NANOELECTROMECHANICAL SYSTEMS - Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions. | 10-25-2012 |
20120286375 | PRESERVING STRESS BENEFITS OF UV CURING IN REPLACEMENT GATE TRANSISTOR FABRICATION - A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. | 11-15-2012 |
20120292602 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 11-22-2012 |
20120306026 | REPLACEMENT GATE ELECTRODE WITH A TUNGSTEN DIFFUSION BARRIER LAYER - A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field. | 12-06-2012 |
20120326228 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 12-27-2012 |
20130020658 | REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 01-24-2013 |
20130029488 | Single Liner Process to Achieve Dual Stress - Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer. | 01-31-2013 |
20130048988 | Nanopillar E-Fuse Structure and Process - Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure. | 02-28-2013 |
20130082348 | Structure and Method to Form Passive Devices in ETSOI Process Flow - Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon. | 04-04-2013 |
20130087759 | Light Emitting Diode (LED) Using Carbon Materials - Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. | 04-11-2013 |
20130087859 | Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 04-11-2013 |
20130093000 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 04-18-2013 |
20130093018 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor. | 04-18-2013 |
20130093021 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor. | 04-18-2013 |
20130095623 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 04-18-2013 |
20130099313 | FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE - FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide. | 04-25-2013 |
20130105894 | THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS | 05-02-2013 |
20130105896 | Threshold Voltage Adjustment For Thin Body Mosfets | 05-02-2013 |
20130115732 | Method to Fabricate Multicrystal Solar Cell with Light Trapping Surface Using Nanopore Copolymer - Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm. | 05-09-2013 |
20130126830 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130130446 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130153964 | FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET. | 06-20-2013 |
20130154001 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130154029 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130168834 | III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 07-04-2013 |
20130175620 | FINFET WITH FULLY SILICIDED GATE - A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. | 07-11-2013 |
20130175632 | REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE - A time clock clearly identifies where a user should position a time card therein. The clock and a printer platen are fixed relative to a base, and has the time card rests thereon. A printing mechanism moves relative to the base and has a target area, it is traversable between a print position and an idle position, and it impresses the time indicia onto the time card while in the print position. A ribbon shield is fixed relative to the base. A focused illuminated guide is fixed relative to the base, and in combination with the ribbon shield, guides the time card with respect to the printing mechanism to clearly identify where the user should position the time card in the time clock. | 07-11-2013 |
20130175633 | CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS - A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure. | 07-11-2013 |
20130175642 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 07-11-2013 |
20130178020 | FINFET WITH FULLY SILICIDED GATE - A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. | 07-11-2013 |
20130200468 | Integration of SMT in Replacement Gate FINFET Process Flow - A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region. | 08-08-2013 |
20130207194 | TRANSISTORS WITH UNIAXIAL STRESS CHANNELS - A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses. | 08-15-2013 |
20130244386 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 09-19-2013 |
20130285156 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 10-31-2013 |
20130307089 | Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 11-21-2013 |
20130309830 | Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 11-21-2013 |
20130328135 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 12-12-2013 |
20130330899 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 12-12-2013 |
20130334602 | CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS - Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed. | 12-19-2013 |
20140042561 | REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 02-13-2014 |
20140061857 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 03-06-2014 |
20140065807 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 03-06-2014 |
20140124861 | TRANSISTORS WITH UNIAXIAL STRESS CHANNELS - A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses. | 05-08-2014 |
20140131802 | Structure and Method to Form Passive Devices in ETSOI Process Flow - Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon. | 05-15-2014 |
20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 06-05-2014 |
20140154851 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element. | 06-05-2014 |
20140191297 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 07-10-2014 |
20140203361 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR FIELD-EFFECT TRANSISTOR WITH AN EPITAXIAL SOURCE AND DRAIN HAVING A LOW EXTERNAL RESISTANCE - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer-on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140203363 | Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140217481 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 08-07-2014 |
20140246727 | WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 09-04-2014 |
20140264444 | STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS - Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure around the periphery of the active area. After formation of a gate stack structure and a gate spacer, trenches are formed such that sidewalls of the trenches are vertically coincident with sidewalls of the gate spacer and the STI spacer. Epitaxial semiconductor material can be deposited into the trenches by selective epitaxy to form an embedded source region and an embedded drain region. Because all surfaces of the trenches are semiconductor surfaces, the entire trenches can be filled with the epitaxial semiconductor material, thereby enabling lateral confinement of stress within a channel region of a field effect transistor. | 09-18-2014 |
20140264558 | FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. | 09-18-2014 |
20140264591 | METHOD AND STRUCTURE FOR DIELECTRIC ISOLATION IN A FIN FIELD EFFECT TRANSISTOR - A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants. | 09-18-2014 |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 10-23-2014 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 10-23-2014 |
20140332860 | STACKED CARBON-BASED FETS - Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions. | 11-13-2014 |
20140332862 | STACKED CARBON-BASED FETS - Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions. | 11-13-2014 |
20140377924 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 12-25-2014 |
20150060770 | Light Emitting Diode (LED) Using Carbon Materials - Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. | 03-05-2015 |
20150069513 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 03-12-2015 |
20150072481 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 03-12-2015 |
20150084096 | FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. | 03-26-2015 |
20150102453 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 04-16-2015 |
20150115365 | CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS - Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed. | 04-30-2015 |
20150187764 | STACKED CARBON-BASED FETS - A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions. | 07-02-2015 |
20150187897 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 07-02-2015 |
20150194334 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 07-09-2015 |
20150194484 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 07-09-2015 |
20150228753 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer. | 08-13-2015 |
20150235903 | Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 08-20-2015 |