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Guo, Cupertino
Hao Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100225655 | Concurrent Encoding/Decoding of Tiled Data - Example embodiments of the present disclosure provide techniques for dividing bitmaps into tiles and processing the tiles concurrently using multiple tile engines. Data compression algorithms may be adapted so that the algorithms can be concurrently processed by multiple data slice engines. The algorithms may be further adapted so that the concurrent outputs for each stage may be passed to the next processing stage without delays or dead cycles. The reduction or elimination of delays or dead cycles may result in a lower latency. | 09-09-2010 |
| 20100226441 | Frame Capture, Encoding, and Transmission Management - Example embodiments of the present disclosure provide techniques for improving the rendering and management of client desktops and the subsequent transmission to the remote client. The techniques may minimize the movement of frame data within the server, the amount of data to be compressed, the amount of data transmitted over the network, and the amount of data to be decompressed. Various embodiments are disclosed for merging rendering functions and encoding functions onto the same chip so that frame data does not need to be transferred, calculation of a tile-based checksum for determining which tiles have changed from frame to frame, the dropping of tiles waiting to be transmitted if network bandwidth or decode speed is limiting the transmission and an equivalent tile in a subsequent frame is available to replace it, and the transfer of the frame buffer into the chip from an external GPU using one of three modes. | 09-09-2010 |
| 20100231599 | Frame Buffer Management - Disclosed are methods and systems for tracking which data tiles have changed within an image frame. In an embodiment, each cell of a tile change list buffer may contain a frame number and updated when a tile is received from encoder. The frame number may be used as a base pointer for a particular frame buffer. When a frame is decoded, the contents of the tile change list buffer may be copied from the current tile change list buffer to the next buffer. This process may reduce memory traffic because the unchanged tile data does not have to be copied from frame to frame. | 09-16-2010 |
Hongwei Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090265669 | LANGUAGE INPUT INTERFACE ON A DEVICE - Methods, systems, devices, and apparatus, including computer program products, for inputting text. A user interface element is presented on a touch-sensitive display of a device. The user interface element is associated with a plurality of characters, at least a subset of which is associated with respective gestures. A user input performing a gesture with respect to the user interface element is received. The character from the subset that is associated with the gesture performed with respect to the user interface element is inputted. | 10-22-2009 |
Jin Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090259886 | APPARATUS AND METHODS FOR RESTORING SYSTEM OPERATION STATES - A process for restoring an operational state of a portable handheld device is provided. The device may include multiple computing units and persistent storage. The operational state may be generated by a sequence of events. The operational state may receive signals corresponding to a plurality of event types. The process may include selecting an event type for storage, storing in the persistent storage events corresponding to the selected event type, receiving a signal indicating an interruption of operation, and transmitting the stored events to restore the device to the operational state. | 10-15-2009 |
| 20110012848 | Methods and apparatus for operating a multi-object touch handheld device with touch sensitive display - A method of performing touch operation on a graphical object on a touch sensitive display of a multi-object touch handheld device is provided. The method comprises detecting the presence of at least two touch input objects; determining one of the touch input objects as pointing at a center of operation; determining a type of operation; and performing the type of operation on the graphical object at the center of operation. A handheld device with at least one processor and at least one type of memory is also provided. The handheld device further comprises touch sensitive display capable of showing at least one graphical object and sensing at least two touch input objects; means for determining the presence of the touch input objects touching the touch sensitive display; and means for determining a center of operation. | 01-20-2011 |
Shuanglin Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080243761 | METHOD AND SYSTEM FOR QUANTIFYING A DATA PAGE REPETITION PATTERN FOR A DATABASE INDEX IN A DATABASE MANAGEMENT SYSTEM - A method and system are presented for quantifying a data page repetition pattern for a database index in a database management system. In one embodiment, the method includes identifying a database index to provide a basis for collecting a data page repetition statistic, the database index having a database index key. The method may also include collecting the data page repetition statistic based on the database index key, wherein the data page repetition statistic quantifies a data page repetition pattern associated with database queries that reference sequential entries of the database index. The method may further include optimizing a data page access process based on the data page repetition statistic. In a further embodiment, the method may utilize both cluster ratio and data page repetition statistics to evaluate data page I/O and CPU cost. | 10-02-2008 |
Ta-Pen Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090315079 | Layout Architecture for Improving Circuit Performance - An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight. | 12-24-2009 |
| 20100078725 | Standard Cell without OD Space Effect in Y-Direction - An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region. | 04-01-2010 |
| 20100127333 | NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT - The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate. | 05-27-2010 |
| 20100164614 | Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules - An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell. | 07-01-2010 |
| 20100281446 | Integrated Circuit Design using DFM-Enhanced Architecture - Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell. | 11-04-2010 |
Wenzhuo Guo, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090004370 | Metal Inks, Methods of Making the Same, and Methods for Printing and/or Forming Metal Films - Printable metal formulations, methods of making the formulations, and methods of coating or printing thin films from metal ink precursors are disclosed. The metal formulation generally includes one or more Group 4, 5, 6, 7, 8, 9, 10, 11, or 12 metal salts or metal complexes, one or more solvents adapted to facilitate coating and/or printing of the formulation, and one or more optional additives that form (only) gaseous or volatile byproducts upon reduction of the metal salt or metal complex to an elemental metal and/or alloy thereof. The formulation may be made by combining the metal salt(s) or metal complex(es) and the solvent(s), and dissolving the metal salt(s) or metal complex(es) in the solvent(s) to form the formulation. Thin films may be made by coating or printing the metal formulation on a substrate; removing the solvents to form a metal-containing precursor film; and reducing the metal-containing precursor film. | 01-01-2009 |
| 20100022078 | Aluminum Inks and Methods of Making the Same, Methods for Depositing Aluminum Inks, and Films Formed by Printing and/or Depositing an Aluminum Ink - Aluminum metal ink compositions, methods of forming such compositions, and methods of forming aluminum metal layers and/or patterns are disclosed. The ink composition includes an aluminum metal precursor and an organic solvent. Conductive structures may be made using such ink compositions by printing or coating the aluminum precursor ink on a substrate (decomposing the aluminum metal precursors in the ink) and curing the composition. The present aluminum precursor inks provide aluminum films having high conductivity, and reduce the number of inks and printing steps needed to fabricate printed, integrated circuits. | 01-28-2010 |