Guillorn
Michael A. Guillorn, Knoxville, TN US
Patent application number | Description | Published |
---|---|---|
20080290326 | Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process - Systems and methods are described for controlled alignment of catalytically grown nanostructures in a large-scale synthesis process. A method includes: generating an electric field proximate an edge of a protruding section of an electrode, the electric field defining a vector; and forming an elongated nanostructure located at a position on a surface of a substrate, the position on the surface of the substrate proximate the edge of the protruding section of the electrode, at least one tangent to the elongated nanostructure i) substantially parallel to the vector defined by the electric field and ii) substantially non-parallel to a normal defined by the surface of the substrate. | 11-27-2008 |
20090081415 | Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process - Systems and methods are described for controlled alignment of catalytically grown nanostructures in a large-scale synthesis process. A method includes: generating an electric field proximate an edge of a protruding section of an electrode, the electric field defining a vector; and forming an elongated nanostructure located at a position on a surface of a substrate, the position on the surface of the substrate proximate the edge of the protruding section of the electrode, at least one tangent to the elongated nanostructure i) substantially parallel to the vector defined by the electric field and ii) substantially non-parallel to a normal defined by the surface of the substrate. | 03-26-2009 |
Michael A. Guillorn US
Patent application number | Description | Published |
---|---|---|
20120108024 | FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL - A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure. | 05-03-2012 |
Michael A. Guillorn, Yorktown Hieghts, NY US
Patent application number | Description | Published |
---|---|---|
20130309837 | PREVENTING SHORTING OF ADJACENT DEVICES - Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins. | 11-21-2013 |