| Patent application number | Description | Published |
|---|
| 20090147578 | Combined volatile nonvolatile array - A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines. | 06-11-2009 |
| 20090168517 | Read and volatile NV standby disturb - A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY. | 07-02-2009 |
| 20090168519 | Architecture of a nvDRAM array and its sense regime - A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface. | 07-02-2009 |
| 20090168520 | 3T high density NVDRAM cell - A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges. | 07-02-2009 |
| 20090168521 | 5T high density NVDRAM cell - A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line. | 07-02-2009 |
| 20090168578 | Dummy cell for memory circuits - A memory cell array includes reference cells each associated with a plurality of data cells of the array. | 07-02-2009 |
| 20100219477 | METHOD FOR THE PRODUCTION OF MOS TRANSISTORS - The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors. This is achieved by initially carrying out an LDD ion implantation via the edges of the gates in order to form an LDD region and subsequently removing the spacers by means of an anisotropic etching step exhibiting high selectivity in relation to the gate and substrate materials, including the covering layers thereof, or by covering the MOS transistors with an extremely low leakage currents prior to isotropic spacer production such that the spacers are formed exclusively on the edges of the gates of the logic/switching transistors, while the MOS transistors with an extremely low leakage current always remain connected solely via the LDD region, and there is no high dose implantation in the S/D regions of these MOS transistors with extremely low leakage currents. | 09-02-2010 |
