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Guarini, US

Kathryn W. Guarini, Yorktown Heights, NY US

Patent application numberDescriptionPublished
20080246090SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE - A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.10-09-2008
20080248616Integration of strained Ge into advanced CMOS technology - A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.10-09-2008

Patent applications by Kathryn W. Guarini, Yorktown Heights, NY US

Kathryn Wilder Guarini, Yorktown Heights, NY US

Patent application numberDescriptionPublished
20080227270LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET CHEMICAL TREATMENT - Described is a wet chemical surface treatment involving NH09-18-2008
20090311851NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.12-17-2009
20110129973NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material.06-02-2011

Patent applications by Kathryn Wilder Guarini, Yorktown Heights, NY US

Theresa Kramer Guarini, San Jose, CA US

Patent application numberDescriptionPublished
20090162570APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE USING INDUCTIVELY COUPLED PLASMA TECHNOLOGY - The present invention generally provides apparatus and methods for processing a semiconductor substrate. Particularly, the present invention provides an inductively coupled plasma reactor having improved process uniformity. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a process volume configured to process the substrate therein, an adjustable coil assembly coupled to the chamber body outside the process volume, a supporting pedestal disposed in the process volume and configured to support the substrate therein, and a gas injection assembly configured to supply a process gas towards a first process zone and a second process zone independently.06-25-2009
20100248435METHOD OF SELECTIVE NITRIDATION - Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.09-30-2010
20100317186ENHANCING NAND FLASH FLOATING GATE PERFORMANCE - Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.12-16-2010
20110011743LOW POWER RF TUNING USING OPTICAL AND NON-REFLECTED POWER METHODS - Aspects of the present invention include methods and apparatuses that may be used for monitoring and adjusting plasma in a substrate processing system by using a plasma data monitoring assembly. In one embodiment, an apparatus for monitoring a plasma in a substrate processing system is provided. The apparatus includes a plasma chamber having a plurality of walls, at least one of the plurality of walls having a dielectric ceiling, at least one inner coil element and at least one outer coil element disposed outside the chamber, a current sensor coupled to one of the inner coil element or the outer coil element, the current sensor adapted to detect current from an inductively coupled plasma generated in the plasma chamber, an RF power source, and one or more adjustable capacitors coupled to each of the one or more coil elements.01-20-2011

Patent applications by Theresa Kramer Guarini, San Jose, CA US