| Patent application number | Description | Published |
|---|
| 20090104770 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10Ω-μm | 04-23-2009 |
| 20110008953 | METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S) - A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal. | 01-13-2011 |
| 20110124170 | PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR - Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess. | 05-26-2011 |
| 20110169124 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm | 07-14-2011 |
| Patent application number | Description | Published |
|---|
| 20090016173 | SPIRAL SPRING MADE OF ATHERMAL GLASS FOR CLOCKWORK MOVEMENT AND METHOD FOR MAKING SAME - The balance spring is made from a photostructurable glass plate by UV irradiation, thermal treatment and etching, said glass having a Young's modulus thermal coefficient CTE | 01-15-2009 |
| 20090237335 | DISPLAY DEVICE ABLE TO OPERATE IN LOW POWER PARTIAL DISPLAY MODE - The display device includes a display cell including liquid crystals and a matrix of electrodes arranged in lines and columns in a closed cavity. The lines and columns define display cell pixels. The display device includes a control circuit for lines and columns for display of data on the display cell. In complete display mode, all lines and columns are addressed at several voltage levels by successive line-by-line multiplexing. In low power partial display mode, two groups of adjacent lines are joined so they are each controlled by a respective line control signal from the control circuit. The N lines and groups of lines are simultaneously addressed in active manner at two voltage levels. N line control signals include a series of N-bit binary line words that change every determined period of time, T, so 2 | 09-24-2009 |
| 20100024930 | ELECTROFORMING METHOD AND PART OR LAYER OBTAINED VIA THE METHOD - The invention concerns an electroformed gold alloy part, characterized in that the gold alloy is made up of 88 to 94% by weight of gold, x % by weight of copper and/or silver, and 2x % by weight of zinc, x being comprised between 2 and 4. | 02-04-2010 |
| 20100308277 | ELECTRICALLY CONDUCTIVE NANOCOMPOSITE MATERIAL COMPRISING SACRIFICIAL NANOPARTICLES AND OPEN POROUS NANOCOMPOSITES PRODUCED THEREOF - Nanocomposites of conductive, nanoparticulate polymer and electronically active material, in particular PEDOT and LiFePO | 12-09-2010 |
| 20110056301 | PRESSURE SENSOR - The invention relates to a pressure sensor ( | 03-10-2011 |
