Patent application number | Description | Published |
20110157737 | Systems and Methods for Detecting a Reference Pattern - Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit. | 06-30-2011 |
20110249361 | FLY-HEIGHT CONTROL USING ASYNCHRONOUS SAMPLING - In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed. | 10-13-2011 |
20120182643 | Systems and Methods for Reduced Format Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples. The zero gain start calculation circuit is operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value. | 07-19-2012 |
20120212851 | Systems and Methods for Medium Contact Detection - Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output. | 08-23-2012 |
Patent application number | Description | Published |
20090323214 | Modulated Disk Lock Clock and Methods for Using Such - Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a storage medium is disclosed that includes calculating a point to point error amount, and generating a incremental error value based at least in part on the point to point error amount. The incremental error value is applied incrementally across a defined number of clock cycles. | 12-31-2009 |
20100142078 | Systems and Methods for Memory Efficient Repeatable Run Out Processing - Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern. | 06-10-2010 |
20100177430 | Systems and Methods for Fly-Height Control Using Servo Address Mark Data - Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium ( | 07-15-2010 |
20100208377 | Systems and Methods for Inter-Location Control of Storage Access - Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a magnetic storage medium is disclosed that includes providing a location count indicating a location between a portion of a first servo data sector of a magnetic storage media and a portion of a second servo data sector of the magnetic storage media, and asserting an enable window signal based upon the location count. | 08-19-2010 |
20100232046 | Methods and Systems for Estimating Time Corresponding to Peak Signal Amplitude - Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude. | 09-16-2010 |
20100271724 | Systems and Methods for Nyquist Tone Harmonic Measurements - Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium, an offset frequency, a read/write head assembly, and a harmonic fly-height change detection circuit. The storage medium includes a periodic data pattern that repeats at a data frequency. The read/write head assembly disposed in relation to the storage medium such that it senses the periodic data pattern and provides a sensed periodic data pattern. The harmonic fly-height change detection circuit samples the sensed periodic data pattern at an aggregate frequency to yield a first set of samples and a second set of samples. The aggregate frequency is the data frequency adjusted by the offset frequency. The harmonic fly-height change detection circuit calculates a first magnitude of the first set of samples and a second magnitude of the second set of samples. | 10-28-2010 |
20110043938 | Systems and Methods for Fly-Height Control Using Servo Data - Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium. | 02-24-2011 |
20120134042 | Systems and Methods for Signal Polarity Determination - Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase. | 05-31-2012 |
20120134043 | Systems and Methods for Spiral Waveform Detection - Various embodiments of the present invention provide systems and methods for determining a location of a spiral pattern. As an example, a location detection circuits is discussed that includes: a pattern detection circuit, a computation circuit, and a center determination circuit. The pattern detection circuit is operable to identify a subset of a series of data samples corresponding to a defined pattern, and to indicate a location of the identified subset of the series of data samples. The series of data samples corresponds to a spiral pattern. The computation circuit operable to sum an absolute value of each sample of the subset of the series of data samples to yield a sum. The center determination circuit operable to identify a location of the spiral pattern using the sum. | 05-31-2012 |
20130003214 | Systems and Methods for Inter-Track Alignment - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track. The offset calculation circuit is operable to calculate an offset between the first track and the second track based at least in part on the first count, the second count, the third count, the fourth count, the fifth count, and the sixth count. | 01-03-2013 |
20130077188 | Systems and Methods for Controlled Wedge Spacing in a Storage Device - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount. | 03-28-2013 |
20130135766 | STORAGE DEVICE HAVING CLOCK ADJUSTMENT CIRCUITRY WITH FIRMWARE-BASED PREDICTIVE CORRECTION - A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop. | 05-30-2013 |
20130148230 | Systems and Methods for Medium Proximity Detection in a Read Channel - A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the aggregated value to an aggregate threshold to yield an aggregate output; and generating a contact event output if one or more of a first group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value and a predefined minimum number of a second group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value. | 06-13-2013 |
20130201576 | STORAGE DEVICE HAVING CALIBRATION CIRCUITRY PROVIDING PROGRAMMABLE PHASE UPDATE VALUES - A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises calibration circuitry configured to vary a phase of a clock signal as a test pattern is written to the storage disk as part of a calibration procedure, and disk locked clock circuitry coupled to the calibration circuitry and configured to obtain phase lock between the clock signal and a timing pattern on a surface of the storage disk. The calibration circuitry is further configured to determine an initial phase update value to be applied by the disk locked clock circuitry in a control loop as the phase of the clock signal is varied as part of the calibration procedure. | 08-08-2013 |
20130201579 | DISK-BASED STORAGE DEVICE WITH HEAD POSITION CONTROL RESPONSIVE TO DETECTED INTER-TRACK INTERFERENCE - A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at least a given track of the storage disk via the read/write head in order to detect interference in that signal from at least one other track of the storage disk. The control circuitry further comprises an inter-track interference based head position controller configured to adjust the positioning of the read/write head responsive to the detected interference. | 08-08-2013 |
20140281818 | Method for Format Savings in Coherently Written Fragmented Sectors - A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment. | 09-18-2014 |