| Patent application number | Description | Published |
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| 20090190431 | Double data rate-single data rate input block and method for using same - A disclosed embodiment is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data into the first input register and a second data into the second input register during a single clock cycle of a system clock, thereby operating at double data input during a single clock cycle. In one embodiment a single data rate/double data rate (SDR/DDR) input block may be operated in either SDR or DDR mode. In one embodiment, the DDR input block may be used with a scannable output reduction block. The DDR input block may be used in systems utilizing a content addressable memory (CAM) or a random access memory (RAM), or other types of memory devices. | 07-30-2009 |
| 20090204739 | Interruptible write block and method for using same - A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register. | 08-13-2009 |
| 20090279340 | N-way mode content addressable memory array - A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data input bus is coupled to each of the M rows. The mode input bus and the data input bus can uniquely identify as a match a single subword or a plurality of subwords in one of the M rows during a search operation. The disclosed embodiment further comprises a row address encoder/generator coupled to each of the M rows, and an address output bus coupled to each of the row address encoder/generators. The mode input bus is also coupled to each of the row address encoder/generators. A uniquely identified single subword address may be outputted on the address output bus. | 11-12-2009 |
| 20100002483 | Range checking content addressable memory array - A disclosed embodiment is a range checking CAM array comprising a plurality of words, where each of the plurality of words comprises a plurality of bound check cells. Each of the plurality of bound check cells outputs a corresponding plurality of match signals and a corresponding plurality of bound check signals. The corresponding plurality of match signals and corresponding plurality of bound check signals are combined to produce a range check output indicating whether data on a data input bus is within a target range. The plurality of bound check cells may be coupled to form at least one cascade of bound check cells, where each cascade of bound check cells may be terminated at a ripple logic. The CAM array produces a final range check output based on the corresponding plurality of match signals and the corresponding plurality of bound check signals. | 01-07-2010 |
| 20100002484 | Content addressable memory array with an invalidate feature - A disclosed embodiment is a CAM (content addressable memory) array with an invalidate feature, the CAM array includes a plurality of words, where each of the plurality of words includes a respective invalidate circuit. Each respective invalidate circuit is configured to invalidate stored data in each corresponding plurality of words if compare data on a data input bus uniquely identifies, i.e. matches, the stored data. Each of the plurality of words is coupled to the data input bus. In one embodiment, each invalidate circuit includes a memory cell which stores a valid bit to configure the invalidate circuit to invalidate the stored data in a respective word. Each of the plurality of words further includes a respective plurality of CAM cells, which store the stored data. Each CAM cell outputs a match signal that is coupled to a latch. The match signals are also coupled to corresponding invalidate circuits. | 01-07-2010 |
