| Patent application number | Description | Published |
|---|
| 20090140246 | METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES - By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency. | 06-04-2009 |
| 20090243116 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence. | 10-01-2009 |
| 20090294921 | SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER - A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity. | 12-03-2009 |
| 20100052134 | 3-D INTEGRATED SEMICONDUCTOR DEVICE COMPRISING INTERMEDIATE HEAT SPREADING CAPABILITIES - In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips. | 03-04-2010 |
| 20100052147 | SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY - By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies. | 03-04-2010 |
| 20100109005 | SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR STRUCTURE FOR DIE INTERNAL MONITORING PURPOSES - In a semiconductor device, electrical measurement data may be obtained with enhanced spatial resolution, for instance from within the entire die region, by providing a distributed sensor structure, each of which may be individually accessed by an appropriate interconnect structure, while nevertheless maintaining the required number of terminals and test signals at a low level. | 05-06-2010 |
| 20100252828 | SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS - A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process. | 10-07-2010 |
