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| 20090116790 | Highly efficient optical gratings with reduced thickness requirements and impedance- matching layers - An optical grating comprising a grating layer and two surface layers, the layers being arranged with the grating layer between the surface layers. The grating layer comprises a set of multiple, discrete, elongated first grating regions that comprise a first dielectric material and are arranged with intervening elongated second grating regions. The bulk refractive index of the dielectric material of the first grating regions is larger than the bulk refractive index of the second grating regions. The first surface layer comprises a first impedance matching layer, and the second surface layer comprises either (i) a second impedance matching layer or (ii) a reflective layer. Each said impedance matching layer is arranged to reduce reflection of an optical signal transmitted through the corresponding surface of the grating layer, relative to reflection of the optical signal in the absence of said impedance matching layer. | 05-07-2009 |
| 20090196551 | MULTIMODE PLANAR WAVEGUIDE SPECTRAL FILTER - A spectral filter comprises a planar optical waveguide having at least one set of diffractive elements. The waveguide confines in one transverse dimension an optical signal propagating in two other dimensions therein. The waveguide supports multiple transverse modes. Each diffractive element set routes, between input and output ports, a diffracted portion of the optical signal propagating in the planar waveguide and diffracted by the diffractive elements. The diffracted portion of the optical signal reaches the output port as a superposition of multiple transverse modes. A multimode optical source may launch the optical signal into the planar waveguide, through the corresponding input optical port, as a superposition of multiple transverse modes. A multimode output waveguide may receive, through the output port, the diffracted portion of the optical signal. Multiple diffractive element sets may route corresponding diffracted portions of optical signal between one or more corresponding input and output ports. | 08-06-2009 |
| 20090285529 | TRANSMISSION GRATINGS DESIGNED BY COMPUTED INTERFERENCE BETWEEN SIMULATED OPTICAL SIGNALS AND FABRICATED BY REDUCTION LITHOGRAPHY - A method comprises computing an interference pattern between a simulated design input optical signal and a simulated design output optical signal, and computationally deriving an arrangement of at least one diffractive element set from the computed interference pattern. The interference pattern is computed in a transmission grating region, with the input and output optical signals each propagating through the transmission grating region as substantially unconfined optical beams. The arrangement of diffractive element set is computationally derived so that when the diffractive element set thus arranged is formed in or on a transmission grating, each diffractive element set would route, between corresponding input and output optical ports, a corresponding diffracted portion of an input optical signal incident on and transmitted by the transmission grating. The method can further comprise forming the set of diffractive elements in or on the transmission grating according to the derived arrangement. | 11-19-2009 |
| 20100327150 | MULTIMODE PLANAR WAVEGUIDE SPECTRAL FILTER - A spectral filter comprises a planar optical waveguide having at least one set of diffractive elements. The waveguide confines in one transverse dimension an optical signal propagating in two other dimensions therein. The waveguide supports multiple transverse modes. Each diffractive element set routes, between input and output ports, a diffracted portion of the optical signal propagating in the planar waveguide and diffracted by the diffractive elements. The diffracted portion of the optical signal reaches the output port as a superposition of multiple transverse modes. A multimode optical source may launch the optical signal into the planar waveguide, through the corresponding input optical port, as a superposition of multiple transverse modes. A multimode output waveguide may receive, through the output port, the diffracted portion of the optical signal. Multiple diffractive element sets may route corresponding diffracted portions of optical signal between one or more corresponding input and output ports. | 12-30-2010 |
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| 20090015233 | DYNAMIC VOLTAGE TRANSITIONS - The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition. | 01-15-2009 |
| 20090089543 | INTEGRATED CIRCUIT PERFORMANCE IMPROVEMENT ACROSS A RANGE OF OPERATING CONDITIONS AND PHYSICAL CONSTRAINTS - Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described. | 04-02-2009 |
| 20090276642 | VOLTAGE REGULATOR WITH SUSPEND MODE - A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state. | 11-05-2009 |
| 20090313489 | INDEPENDENT POWER CONTROL OF PROCESSING CORES - Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores. | 12-17-2009 |
| 20110022865 | INDEPENDENT POWER CONTROL OF PROCESSING CORES - Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores. | 01-27-2011 |
| 20110133720 | DYNAMIC VOLTAGE TRANSITIONS - The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition. | 06-09-2011 |
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| 20100138683 | POWER CONTROL UNIT WITH DIGITALLY SUPPLIED SYSTEM PARAMETERS - Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element. | 06-03-2010 |
| 20100174936 | Communicating Via An In-Die Interconnect - In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed. | 07-08-2010 |
| 20100262823 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 10-14-2010 |
| 20100281255 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 11-04-2010 |
