| Patent application number | Description | Published |
|---|
| 20080258219 | Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer - A semiconductor device is provided which comprises a semiconductor layer ( | 10-23-2008 |
| 20080268587 | Inverse slope isolation and dual surface orientation integration - A semiconductor process and apparatus provide a high performance CMOS devices ( | 10-30-2008 |
| 20080274594 | Step height reduction between SOI and EPI for DSO and BOS integration - A semiconductor process and apparatus provides a planarized hybrid substrate ( | 11-06-2008 |
| 20080274595 | Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation - A semiconductor process and apparatus provide a planarized hybrid substrate ( | 11-06-2008 |
| 20080299750 | MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION - A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time. | 12-04-2008 |
| 20100230756 | SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION - A semiconductor device is provided which comprises a semiconductor layer ( | 09-16-2010 |
| 20100276735 | SEMICONDUCTOR DEVICE WITH PHOTONICS - A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer. | 11-04-2010 |
| 20110027950 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR - A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material. | 02-03-2011 |
