| Patent application number | Description | Published |
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| 20080237886 | Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions - Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array. | 10-02-2008 |
| 20080238478 | FPGA architecture at conventonal and submicron scales - Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array. | 10-02-2008 |
| 20080258767 | Computational nodes and computational-node networks that include dynamical-nanodevice connections - Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies. | 10-23-2008 |
| 20090189642 | Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions - Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a method for implementing a logic gate comprises: providing a first layer of approximately parallel nanowires; interconnecting the first layer of approximately parallel nanowires with a second layer of approximately parallel nanowires through configurable, tunneling resistor junctions; selecting nanowires from among the first and second layer of nanowires to carry input and output electrical signals representing logical values; applying electrical signals representing input logical values to the input nanowires; and detecting an electrical signal representing an output logical value on the output nanowires. | 07-30-2009 |
| 20090196090 | Nanoscale Shift Register And Signal Demultiplexing Using Microscale/Nanoscale Shift Registers - Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar. | 08-06-2009 |
| 20100081238 | MIXED-SCALE ELECTRONIC INTERFACE - Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer. | 04-01-2010 |
