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| 20090060941 | Methods for the treatment of diabetes, the reduction of body fat, improvement of insulin sensitivity, reduction of hyperglycemia, and reduction of hypercholesterolemia with chromium complexes, conjugated fatty acids, and/or conjugated fatty alcohols - A composition for treating insulin-dependent diabetes, reducing body fat, improving insulin sensitivity, reducing hyperglycemia, and reducing hypercholesterolemia with at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol is disclosed. A method of treating a subject suffering from insulin-dependent diabetes by administering a composition that includes at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol is similarly provided. The administration of a composition containing an effective dose of at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol for the treatment of obesity is likewise provided. | 03-05-2009 |
| 20090136539 | Methods for the treatment of diabetes, the reduction of body fat, improvement of insulin sensitivity, reduction of hyperglycemia, and reduction of hypercholesterolemia with chromium complexes, conjugated fatty acids, and/or conjugated fatty alcohols - A composition for treating insulin-dependent diabetes, reducing body fat, improving insulin sensitivity, reducing hyperglycemia, and reducing hypercholesterolemia with at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol is disclosed. A method of treating a subject suffering from insulin-dependent diabetes by administering a composition that includes at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol is similarly provided. The administration of a composition containing an effective dose of at least one chromium complex and a conjugated fatty acid or conjugated fatty alcohol for the treatment of obesity is likewise provided. | 05-28-2009 |
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| 20080318373 | Method of fabricating self-aligned bipolar transistor having tapered collector - A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions. | 12-25-2008 |
| 20090134429 | TRANSISTOR STRUCTURE WITH MINIMIZED PARASITICS AND METHOD OF FABRICATING THE SAME - A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided. | 05-28-2009 |
| 20100176453 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER - A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed. | 07-15-2010 |
| 20100176482 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION - A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed. | 07-15-2010 |
| 20100187607 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER - A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed. | 07-29-2010 |
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| 20080237648 | MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP - Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow. | 10-02-2008 |
| 20090190640 | Radio Frequency Integrated Circuit with On-Chip Noise Source for Self-Test - Radio frequency integrated circuits with on-chip noise source for use in the performance of tests and/or calibrations. For example, a radio frequency integrated circuit comprises at least one noise source residing on the radio frequency integrated circuit, the noise source being controllable by a digital input, and a radio frequency circuit residing on the radio frequency integrated circuit and being coupled to the noise source, wherein at least one attribute of the radio frequency circuit is determinable by controlling the noise source via the digital input. | 07-30-2009 |
| 20090278207 | Electromigration-Complaint High Performance FET Layout - An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor. | 11-12-2009 |
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| 20080307374 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MAPPING A LOGICAL DESIGN ONTO AN INTEGRATED CIRCUIT WITH SLACK APPORTIONMENT - A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable. If the timing slack is not acceptable, the slack is apportioned for, and apportioned slack information is fed back in the form of timing assertions. Mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the timing slack associated with each temporary logical partition is determined to be acceptable. | 12-11-2008 |
| 20090245008 | SYSTEM AND METHOD FOR PROVIDING VOLTAGE POWER GATING - A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state. | 10-01-2009 |
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| 20090288965 | Container with secondary substance, preferably a liquid for attachment to and mixing with container of a primary liquid - An apparatus for adding a secondary substance to a primary liquid within a sealed container, for example, a shot of liquor to be added to a can of soda. A secondary container contains the secondary substance preferably a liquid and has a frangible seal. A mechanism sealingly and mechanically attaches the secondary container to the hull of a primary container having primary liquid. A frangible seal is provided to the secondary container. A penetrator is disposed at least partially within the housing of the secondary container and is at least partially surrounded by the attachment mechanism. —The penetrator causes rupture of the seal and mechanically penetrates through the hull of the primary container. The substance from the secondary container mixes with the liquid of the primary container. The secondary container may attach to the top, side, or bottom of a conventional primary container, a soda can. | 11-26-2009 |
| 20100100236 | Vending machines with lighting interactivity and item-based lighting systems for retail display and automated retail stores - Vending machines, automated retail stores, and retail displays with computer controlled, item-based lighting that produces variable visual effects in conjunction with actual or potential vends to provide an enhanced vending experience. Offered products are stored within display tubes that are arranged in orderly geometric arrays. RGB lighting through a plurality of LED banks within polygonal circuit boards associate with each display tube are controlled by a computer activation system that senses the presence of a customer, and the selection of a vend. Combinations of differently colored LED's are computer controlled on a per product basis to artistically illuminate available products and assist customers. Pre-programmed lighting sequences can switch LED off and on, vary their intensity, and alter resultant colors. A touch screen computer responds to user inputs for selections and transactions. Sensors detect the presence of potential customers, even without a customer input, to vary a display and attract mode. | 04-22-2010 |
| 20100103131 | Interactive and 3-D multi-senor touch selection interface for an automated retail store, vending machine, digital sign, or retail display - Vending machines, automated retail stores, and retail displays with a computer controlled, activation system that senses either the gesture of a customer proximate product display tubes or a touch-screen selection on a computer screen. Item-based lighting produces variable visual effects in conjunction with actual or potential vends to provide an enhanced vending experience. Offered products are stored within display tubes that are arranged in orderly geometric arrays. RGB lighting through a plurality of LED banks associated with each display tube are controlled by the activation system Combinations of differently colored LED's are computer controlled on a per product basis to artistically illuminate available products and assist customers. Pre-programmed lighting sequences can switch LEDs off and on, vary their intensity, and alter resultant colors. | 04-29-2010 |
| 20100262282 | Customer retention system and process in a vending unit, retail display or automated retail store - A vending system comprising numerous remote vending machines, retail displays, and automated retail stores connected to a communication network access a central database so that each remote machine provides and responds to personalized customer information. Each machine comprises a display containing products to be vended and a plurality of touchable product viewing areas for initiating a vend. A computer recognizes customer data derived from peripheral inputs. Software communicates with the database for establishing customer profiles and either recognizing customers or registering customers by generating a global unique identifier. Subroutines initiate the dispensing of items in response to preselected conditions associated with each GUID. | 10-14-2010 |
| 20110054673 | Modular vending with centralized robotic gantry - A vending arrangement for computerized vending machines, retail displays, automated retail stores, utilizes a centralized, robotic gantry associated with companion modules for vending a plurality of selectable products. The modularized design enables deployment of half-sized or larger, full sized machines. The robotic gantry is deployed in a centralized module disposed adjacent display and inventory modules. Inventory modules can be fitted to both gantry sides, and doors can be fitted to the gantry front or rear. The gantry comprises an internal, vertically displaceable elevator utilizing a central conveyor for laterally, horizontally moving selected items from associated display and inventory positions to a vending position. Computerized software enables the display and vending functions, and controls elevator movement to dispense products from twin sides of the gantry by appropriately controlling the conveyor. | 03-03-2011 |
