| Patent application number | Description | Published |
|---|
| 20080204108 | DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES - A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal. | 08-28-2008 |
| 20090025204 | MICROSTRIP LINE DIELECTRIC OVERLAY - A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed circuit board. A dielectric coating is applied to at least one of the at least two microstrip lines such that the dielectric constant of the dielectric coating differs from the dielectric constant of free space. In a further embodiment, the dielectric coating comprises a material having a dielectric constant approximately equal to the dielectric constant of the printed circuit board. | 01-29-2009 |
| 20090070503 | CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate. | 03-12-2009 |
| 20090184745 | DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES - A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal. | 07-23-2009 |
| 20090276545 | MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS - A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output. | 11-05-2009 |
| 20100223406 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS - Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback. | 09-02-2010 |
| 20110140858 | METHODS AND APPARATUS FOR RFID TAG COMMUNICATIONS - The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal. | 06-16-2011 |
| 20110145453 | CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate. | 06-16-2011 |
| Patent application number | Description | Published |
|---|
| 20090109041 | RFID LABEL TIME SYNCHRONIZATION - Methods and apparatus, including computer program products, for radio frequency identification (RFID) label time synchronization. A method includes, in a radio frequency identification (RFID) interrogator having an antenna, transceiver, a clock, a memory and a central processing unit (CPU), initializing a RFID tag with a label start time and a time to record data, the label start time representing an actual start time indicated by the clock, receiving a label stop time, a label time and logged data from an interrogation of the RFID tag, and compensating the label time for a drift between the label stop time and an actual stop time. | 04-30-2009 |
| 20090128292 | RFID DEVICE TIME SYNCHRONIZATION FROM A PUBLIC SOURCE - A radio frequency identification (RFID) device includes an antenna linked to a receiving circuit, the antenna tuned to receive a radio frequency (RF) time-code signal from a public source, a controller circuit and an internal clock linked to the receiving circuit, a microcontroller linked to the receiving circuit, a memory linked to the microcontroller, and a battery linked to and powering the receiving circuit, controller circuit, internal clock, microcontroller and memory. | 05-21-2009 |
| 20090284377 | Flexible RFID Label - A radio frequency identification (RFID) tag includes a base supporting an integrated circuit and a first antenna orthogonal to a second antenna, the first antenna and the second antenna coupled to the integrated circuit, and a first fold in the base that when creased, defines two lobes lying in two planes, a first lobe including a first portion of the first antenna positioned in an x-axis relative to the second antenna oriented along a y-axis, and a second lobe including a second portion of the first antenna positioned in a z-axis relative to the first portion of the first antenna and second antenna. | 11-19-2009 |
| 20110133897 | RFID Device Time Synchronization From A Public Source - A radio frequency identification (RFID) device includes an antenna linked to a receiving circuit, the antenna tuned to receive a radio frequency (RF) time-code signal from a public source, a controller circuit and an internal clock linked to the receiving circuit, a microcontroller linked to the receiving circuit, a memory linked to the microcontroller, and a battery linked to and powering the receiving circuit, controller circuit, internal clock, microcontroller and memory. | 06-09-2011 |
