| Patent application number | Description | Published |
|---|
| 20080267542 | Zipper with fold over elements for reclosable package - A zipper assembly for a reclosable package or bag is disclosed. The zipper assembly includes two profiles with flanges and internal interlocking elements on the interior of the flanges. The exterior of one of the flanges includes two exterior parallel press-to-close profile-like interlocking elements which are brought into engagement with each other by folding the flanges of the zipper assembly. This increases the burst handling capability of the zipper assembly and the package or bag to which it is attached. Alternatives include substituting a peel seal for the exterior interlocking element as well as an exterior label or sticker to maintain the flanges in a folded configuration. | 10-30-2008 |
| 20080279484 | Leak-proofing gussets on multi-wall paper and woven polypropylene packages or bags - Reclosable gusseted packages or bags have improved resistance to leaking or spilling through the gussets by way of glue or adhesive applied in the gussets in the areas proximate to the reclosable zipper of the bag. This can be done by applying a glue smear to the interior and exterior of the gusset walls; applying glue dots between the exterior facing walls of the gussets; or by applying the glue smear between the exterior facing walls of the gussets. | 11-13-2008 |
| 20100278457 | ARCHING ZIPPER AND METHOD OF MANUFACTURE - Zippers are provided for reclosable packages or bags. By selectively co-extruding a first portion of the zipper with a shrinkable or expandable material, and simultaneously co-extruding a second portion of the zipper with a dimensionally stable thermoplastic or similar material, followed by a step of activating the shrinkage or expansion of the shrinkable material, several different shapes of zipper can be achieved. For instance, by co-extruding the shrinkable material to a lower portion of the zipper or co-extruding the expandable material to an upper portion of the zipper, an upwardly arching or convex shape can be achieved. Similarly, by co-extruding the shrinkable material to an upper portion of the zipper or co-extruding the expandable material to a lower portion of the zipper, a downwardly arching or concave shape can be achieved. Similarly, by co-extruding the shrinkable material to inner portions of the zipper or the expandable material to outer portions of the zipper, a self-opening characteristic may be added to the zipper. Additionally, zippers may be placed at inclined positions in a complementary head-to-head configuration in order to eliminate or reduce waste of packaging material during manufacture. | 11-04-2010 |
| 20110185680 | ADDING MASS TO SLIDER END STOMPS WITH ULTRASONICS IN A RECLOSABLE PACKAGE - The disclosure relates to a method and apparatus wherein extra mass is added to a profile of a slider zipper prior to the ultrasonic or thermal forming of the end stomps. This results in an end stomp of increased size and height, thereby providing a greater resistance to the slider being pulled from the ends of the zipper. | 08-04-2011 |
| Patent application number | Description | Published |
|---|
| 20090265673 | INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN - A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data. | 10-22-2009 |
| 20090265679 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 10-22-2009 |
| 20100031221 | VIA DENSITY CHANGE TO IMPROVE WAFER SURFACE PLANARITY - Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface. | 02-04-2010 |
| 20100032846 | IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD - An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer. | 02-11-2010 |
| 20100077372 | Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design - Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction. | 03-25-2010 |
| 20110184715 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 07-28-2011 |
