| Patent application number | Description | Published |
|---|
| 20090141011 | Systems and Methods for Driving Multiple Displays Using a Common Display Driver - Various systems and methods for implementing multi-display driver systems are disclosed. As one example, a display system is disclosed that includes a display driver, a processor, a computer readable medium, and a splitter device. The computer readable medium includes instructions executable by the processor to configure the display driver to provide a display output set for a virtual display. The splitter device is operable to receive at least a portion of a display output set, and to provide a first display output to drive a first display and a second display output to drive a second display based on the portion of the display output set. | 06-04-2009 |
| 20100085096 | ENERGY-EFFICIENT CLOCK SYSTEM - A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time. | 04-08-2010 |
| 20100088446 | PRIORITIZING INTERRUPT CONTROLLER - A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports. | 04-08-2010 |
| 20100088542 | LOCKUP RECOVERY FOR PROCESSORS - A system comprises processing logic configured to assert a lockup signal upon detection of a fault condition and a module coupled to the processing logic and configured to activate a counter upon receiving the lockup signal. After the module activates the counter and before the counter reaches a predetermined threshold, the processing logic attempts to correct the fault condition and the module prevents the processing logic from being reset. | 04-08-2010 |
| 20100088563 | SAVING DEBUGGING CONTEXTS WITH PERIODIC BUILT-IN SELF-TEST EXECUTION - A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic. | 04-08-2010 |
| 20100088760 | DEBUG SECURITY LOGIC - A system comprises debug logic usable to debug the system. The system also comprises processing logic capable of accessing the debug module using electronic signals. The system further comprises security logic configured to prevent the processing logic from accessing the debug logic unless the security logic is provided with a passkey that matches another passkey stored in the system. | 04-08-2010 |
