Greb, US
Karl F. Greb, Missouri City, TX US
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20090141011 | Systems and Methods for Driving Multiple Displays Using a Common Display Driver - Various systems and methods for implementing multi-display driver systems are disclosed. As one example, a display system is disclosed that includes a display driver, a processor, a computer readable medium, and a splitter device. The computer readable medium includes instructions executable by the processor to configure the display driver to provide a display output set for a virtual display. The splitter device is operable to receive at least a portion of a display output set, and to provide a first display output to drive a first display and a second display output to drive a second display based on the portion of the display output set. | 06-04-2009 |
20100085096 | ENERGY-EFFICIENT CLOCK SYSTEM - A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time. | 04-08-2010 |
20100088446 | PRIORITIZING INTERRUPT CONTROLLER - A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports. | 04-08-2010 |
20100088542 | LOCKUP RECOVERY FOR PROCESSORS - A system comprises processing logic configured to assert a lockup signal upon detection of a fault condition and a module coupled to the processing logic and configured to activate a counter upon receiving the lockup signal. After the module activates the counter and before the counter reaches a predetermined threshold, the processing logic attempts to correct the fault condition and the module prevents the processing logic from being reset. | 04-08-2010 |
20100088563 | SAVING DEBUGGING CONTEXTS WITH PERIODIC BUILT-IN SELF-TEST EXECUTION - A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic. | 04-08-2010 |
20100088760 | DEBUG SECURITY LOGIC - A system comprises debug logic usable to debug the system. The system also comprises processing logic capable of accessing the debug module using electronic signals. The system further comprises security logic configured to prevent the processing logic from accessing the debug logic unless the security logic is provided with a passkey that matches another passkey stored in the system. | 04-08-2010 |
20120173933 | PROFILE-BASED EXECUTION MONITORING - An error monitor receives a first list of selected system events with each selected system event having an associated range. The occurrence of each selected system event is counted over a selected time period. An error indication is provided based on a comparison of each of the counts of the occurrence of each selected system event over the selected time period with the associated range. Operational profiles are used to store lists of selected system events with each selected system event having an associated range for each operational profile. | 07-05-2012 |
Karl F. Greb, Sugar Land, TX US
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20120319725 | TESTING FOR MULTIPLEXER LOGIC ASSOCIATED WITH A MULTIPLEXED INPUT/OUTPUT PIN - An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux. | 12-20-2012 |
20150029344 | VIDEO OUTPUT SUPERVISOR - A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved displaying safety-critical data in the data frame to be displayed can be supervised for the presence and status of display indicators of the safety-critical data. The confidence of the supervision can be increased by measuring other display and frame parameters in conjunction with supervising the indicators of the safety-critical data. | 01-29-2015 |
Karl Fredrich Greb, Sugarland, TX US
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20140223052 | SYSTEM AND METHOD FOR SLAVE-BASED MEMORY PROTECTION - A system includes a bus slave coupled to a plurality of bus masters via one or more interconnects. The system also includes a memory protection unit (MPU) associated with the bus slave, the MPU having a set of access permissions that grants access to the bus slave from a first bus master and denies access to the bus slave from a second bus master. The MPU generates an error response as result of a transaction generated by a task on the second bus master attempting to access the bus slave. | 08-07-2014 |
Karl Friedrich Greb, Sugar Land, TX US
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20140173548 | Tool For Automation Of Functional Safety Metric Calculation And Prototyping Of Functional Safety Systems - A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool then automatedly performs a functional safety analysis based on the information regarding the user's specific implementation of the integrated circuit device. In one embodiment, the customer specifies specific functional modules of the integrated circuit device, and the tool performs a functional safety analysis of the integrated circuit device that considers the functional modules selected by the user. In another embodiment, the customer specifies diagnostic measures that are implemented in the user's application of the integrated circuit device, and the tool automatedly performs a functional safety analysis of the integrated circuit device taking into account the diagnostic measures selected by the user. | 06-19-2014 |
20140223047 | SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMMABLE BUS MASTER - A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task. | 08-07-2014 |
20140223127 | SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION - A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented. | 08-07-2014 |
Karl Friedrich Greb, Sugarland, TX US
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20120173924 | DUAL ENDIANESS AND OTHER CONFIGURATION SAFETY IN LOCK STEP DUAL-CORE SYSTEM, AND OTHER CIRCUITS, PROCESSES AND SYSTEMS - An electronic circuit includes a microcontroller processor ( | 07-05-2012 |
Karl Friedrich Greb, Missouri City, TX US
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20120066551 | Run-time Verification of CPU Operation - Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum. | 03-15-2012 |
20120166880 | INDEPENDENTLY BASED DIAGNOSTIC MONITORING - An independently based diagnostic system tests the execution of a processor. The processor is arranged to provide a diagnostic output that provides a pre-determined time-variant signal. The independently based diagnostic system has an independent basis from which to evaluate the pre-determined time-variant signal. The independent basis can be, for example, an independent time base that is separately generated from the processor time base used to clock the processor and/or an independent voltage source that is separate from the processor power supply. The independently based diagnostic system provides progressive notifications of the results of successive evaluations of the pre-determined time-variant signal. | 06-28-2012 |
20120226949 | Multi-Channel Bus Protection - An embodiment of the invention provides a method for managing errors on a bus. Information read from a source is encoded. The encoded information is transmitted on a channel that is part of the bus. The encoded information is evaluated. When no errors are detected, the decoded information is provided to a target. When the decoded information has an error or errors that can not be corrected, the source is asked to present the information to the bus again. When an error or errors can be corrected, the corrected information is sent to the target. | 09-06-2012 |
Karl Friedrich Greb, Fort Bend, TX US
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20150143181 | DUAL ENDIANESS AND OTHER CONFIGURATION SAFETY IN LOCK STEP DUAL-CORE SYSTEM, AND OTHER CIRCUITS, PROCESSES AND SYSTEMS - An electronic circuit includes a microcontroller processor ( | 05-21-2015 |
Richard G. Greb, Raleigh, NC US
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20090257741 | Stabilizer Device for Optical Equipment - A stabilizer for a hand-held optical device includes a gyroscope assembly suspended below a base assembly, and a handle pivotably attached to the base assembly. The optical device, which may be a video camera, mounts to the base assembly. The gyroscope assembly has two or more rotatable members that pivot independently to stabilize the optical device about two or more axes of rotation whenever the user moves the stabilizer. A rigid strut connects the gyroscope to the base assembly such that the centers of rotation of the rotatable members are co-linear with a longitudinal axis that extends the handle. | 10-15-2009 |
20100238345 | Adjustable Control for an Inertial Stabilizer - A handle assembly connects to a support assembly of an inertial stabilizer. The handle assembly comprises a handle grip, a multi-axis joint that allows the handle grip to move relative to the support assembly about two or more axes of rotation, and an adjustable friction control that allows a user to adjust or vary an amount of friction that is applied to the axes of rotation. Allowing the user to increase and decrease the amount of friction applied to the axes of rotation in a controlled manner allows the user to effectively isolate the inertial stabilizer from the undesirable effects of user motion. | 09-23-2010 |
Scott Greb, Washington Township, MI US
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20120181728 | INJECTION MOLDING NOZZLE - An injection molding nozzle for dispensing of molten material includes an elongated body member having an outer surface, a first portion at a proximal end, a second portion at a distal end, and a central passageway extending longitudinally therethrough from the first portion to the second portion. The central passageway includes an inlet defined at the proximal end and splits outwardly at the second portion to form a radially extending passageway leading to an outlet. A tip member is coupled to the outlet to facilitate dispensing of molten material into a mold cavity. A groove is defined on the outer surface of the body member that winds from the first portion to a heated section of the second portion that is positioned adjacent to the tip member. | 07-19-2012 |