Patent application number | Description | Published |
20120314522 | CONTROLLING CLOCK INPUT BUFFERS - An integrated circuit may have a clock input pin coupled to a buffer ( | 12-13-2012 |
20140122814 | APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES - Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received. | 05-01-2014 |
20140122822 | APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES - Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation. | 05-01-2014 |
20140281182 | APPARATUSES AND METHODS FOR VARIABLE LATENCY MEMORY OPERATIONS - Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period. | 09-18-2014 |
20140340135 | CONTROLLING CLOCK INPUT BUFFERS - An integrated circuit may have a clock input pin coupled to a buffer ( | 11-20-2014 |
20150052288 | APPARATUSES AND METHODS FOR PROVIDING DATA FROM A BUFFER - Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command. | 02-19-2015 |
20150052299 | APPARATUSES AND METHODS FOR PROVIDING DATA TO A CONFIGURABLE STORAGE AREA - Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command. | 02-19-2015 |
20150100744 | METHODS AND APPARATUSES FOR REQUESTING READY STATUS INFORMATION FROM A MEMORY - Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information. | 04-09-2015 |