Grant P.

Grant P. Gruetzmacher, Manassas Park, VA US

Patent application number	Description	Published
20100008593	Method and apparatus for model compression - Aspects of the disclosure provide a lossless compression method for 3D mesh models. The method can be combined or layered with other compression methods to provide additional data compression capability. The method for compressing a mesh model having geometry information and connectivity information of vertices can include defining a first set of vertices having a same connectivity property, determining a subset of the first set of vertices that are encompassed by an area defined by the first set of vertices, and encoding the mesh model without the connectivity information for the subset of the first set of vertices.	01-14-2010

Patent application number	Description	Published
20090108879	PROGRAMMABLE SENSITIVITY FREQUENCY COINCIDENCE DETECTION CIRCUIT AND METHOD - A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.	04-30-2009

Patent application number	Description	Published
20110298474	IMPLEMENTING INTEGRAL DYNAMIC VOLTAGE SENSING AND TRIGGER - A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.	12-08-2011