Patent application number | Description | Published |
20080282060 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 11-13-2008 |
20090049269 | HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR - A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory. | 02-19-2009 |
20090055624 | CONTROL OF PROCESSING ELEMENTS IN PARALLEL PROCESSORS - The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines. | 02-26-2009 |
20100318765 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 12-16-2010 |
20110010507 | HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR - A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory. | 01-13-2011 |
20120239907 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 09-20-2012 |
Patent application number | Description | Published |
20090190006 | Methods, systems and apparatuses for pixel signal correction using elliptical hyperbolic cosines - Methods, systems and apparatuses for correcting the sensitivity of pixel signals, the pixel signal correction values being determined based on an elliptical hyperbolic cosine function. The function may further be a rotated elliptical hyperbolic cosine function or a polynomial derived from the rotated elliptical hyperbolic cosine function. Using these functions to represent the correction values in memory allows for on-chip storage of the means to determine the correction values. | 07-30-2009 |
20100014770 | Method and apparatus providing perspective correction and/or image dewarping - Methods and apparatuses for providing dewarping and/or perspective correction of an input image are disclosed. Described embodiments include processing that provides dewarping and/or perspective correction by associating pixel values identified by input pixel addresses corresponding to an input image with output pixel addresses corresponding to an output image. An image processor having a storage circuit and an address mapping unit for determining a corresponding input pixel address from an output pixel address is also disclosed. | 01-21-2010 |
20100070738 | FLEXIBLE RESULTS PIPELINE FOR PROCESSING ELEMENT - A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighbourhood connection register configured to receive data from and send data to other processing elements. The connections between the result registers and between the result registers and the neighbourhood connection register are selectively configurable by applied control signals. | 03-18-2010 |
20100315523 | OBJECT DETECTION USING AN IN-SENSOR DETECTOR - Systems and methods are provided for detecting an object of object class, such as faces, in an image sensor. In some embodiments, the image sensor can provide a scan sequence that scans a scene over multiple time intervals. The image sensor can scan, in succession, portions of a scene, where each of the portions covers a different amount or location of the scene. This way, the scanned portions can be saved in an image buffer that is sized significantly smaller than an entire frame. In some embodiments, when the image sensor detects the presence of an object of the object class, the image sensor can store positional information (e.g., location and size of the object) in a region of interest buffer. The image sensor can output the positional information to aid an electronic device, such as a camera, perform various functions, such as automatic exposure and color balancing. | 12-16-2010 |
20100316254 | USE OF Z-ORDER DATA IN AN IMAGE SENSOR - Systems and methods are provided for detecting objects of an object class, such as faces, in an image sensor. In some embodiments, the image sensor can include a detector with an image buffer. The image buffer can store image data in raster order. The detector can read the data out in Z order to perform object detection. The image data can then compute feature responses using the Z-ordered image data and determine whether any objects of the object class are present based on the feature responses. In some embodiments, the detector can downscale the image data while the object detection is performed and use the downscaled image data to continue the detection process. In some embodiments, the image data can perform detection even if the image is rotated. | 12-16-2010 |
Patent application number | Description | Published |
20110182474 | EFFICIENT SYSTEM AND METHOD FOR FACE TRACKING - A method of scanning a scene using an image sensor includes (a) dividing the scene into multiple first portions; and scanning a first portion for presence of objects in an object class. The method further includes continuing the scanning of the multiple first portions for presence of other objects in the scene. The method also selects a second portion of the scene, in response to detecting an object in the first portion; and then tracking the object in the selected second portion. The second portion of the scene is selected based on estimating motion of the object detected in the first portion, so that it may still be located in the second portion. | 07-28-2011 |
20120182442 | HARDWARE GENERATION OF IMAGE DESCRIPTORS - Interest point and description circuitry is provided for tracking an object through multiple image frames. Interest point and description circuitry may be provided on an integrated circuit in an imaging device. Interest points and descriptors may be calculated at frame rate. A feature detection function may be applied to scaled images to extract interest points. Descriptors may be rotating circular gradient-histogram descriptors. Descriptors may have one or two rings, each having equal area. Descriptors may have discrete rotational positions and discrete scaling. Gradient-histograms may be calculated for the descriptors using angular, radial, and directional weighting components. | 07-19-2012 |
20120183224 | INTEREST POINT DETECTION - Interest points are markers anchored to a specific position in a digital image of an object. They are mathematically extracted in such a way that, in another image of the object, they will appear in the same position on the object, even though the object may be presented at a different position in the image, a different orientation, a different distance or under different lighting conditions. Methods are disclosed that are susceptible to implementation in hardware and corresponding hardware circuits are described. | 07-19-2012 |
20120188329 | SYSTEMS FOR VERTICAL PERSPECTIVE CORRECTION - Systems are provided for vertical perspective correction during image processing. An image processor may receive an input image from an image sensor and output a lower resolution output image that may be suitable for transmission during videoconferencing. Triangular portions of an input image may be masked to produce a trapezoidal masked image. The trapezoidal masked image may be horizontally scaled using a varying horizontal scale factor. The image may be vertically scaled using a vertical scale factor. | 07-26-2012 |
20120274627 | SELF CALIBRATING STEREO CAMERA - A self calibrating stereo camera includes first and second spatial transform engines for directly receiving first and second images, respectively, of an object. The first and second spatial transform engines are coupled to a stereo display for displaying a fused object in stereo. A calibration module is coupled to the first and second spatial transform engines for aligning the first and second images, prior to display to a viewer. The first and second point extracting modules, respectively, receive the first and second images for extracting interest points from each image. A matching points module is coupled to the first and second point extracting modules for matching the interest points extracted by the first and second point extracting modules. The calibration module determines alignment error between the first and second images, in response to the interest point matches calculated by the matching points module. | 11-01-2012 |
20130070139 | IMAGE SENSOR WITH FLEXIBLE INTERCONNECT CAPABILITIES - Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked. | 03-21-2013 |