Patent application number | Description | Published |
20080244191 | Processor system management mode caching - In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described. | 10-02-2008 |
20090006658 | Deferring peripheral traffic with sideband control - In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described. | 01-01-2009 |
20090006704 | Deferring Peripheral traffic with sideband control - In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described. | 01-01-2009 |
20090172434 | Latency based platform coordination - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 07-02-2009 |
20110078473 | LATENCY BASED PLATFORM COORDINATION - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 03-31-2011 |
20110302626 | LATENCY BASED PLATFORM COORDINATION - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 12-08-2011 |
20140181559 | SUPPORTING RUNTIME D3 AND BUFFER FLUSH AND FILL FOR A PERIPHERAL COMPONENT INTERCONNECT DEVICE - Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means for determining that the device should change power states, and means for sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state. In an embodiment, the device is a peripheral component interconnect (PCI) device. Also, the particular example implementation can include means for sending a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller. In some embodiments, the WAKE# signal is not sent to other devices in the system. | 06-26-2014 |
Patent application number | Description | Published |
20130151569 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 06-13-2013 |
20140059337 | COMPUTING PERFORMANCE AND POWER MANAGEMENT WITH FIRMWARE PERFORMANCE DATA STRUCTURE - In some embodiments, a PPM interface for a computing platform may he provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data. | 02-27-2014 |
20140181563 | SYSTEM AND METHOD FOR DETERMINATION OF LATENCY TOLERANCE - Particular embodiments described herein can offer a method that includes determining that a first reported latency tolerance associated with at least one first device has not been received, and causing determination of a platform latency tolerance based, at least in part, on a first predefined latency tolerance, which is to serve as a substitute for the first reported latency tolerance. | 06-26-2014 |
20140189184 | CREATING DYNAMIC FIXED FUNCTIONALITY FOR A HARDWARE DEVICE SYSTEM - One particular example implementation of an apparatus that includes logic, the logic at least partially comprising hardware logic to: trigger a particular interrupt based, at least in part, on input/output (I/O) activity when a predetermined state is activated on a platform; generate a system control interrupt based, at least in part, on a source associated with the particular interrupt; and route the system control interrupt to a custom system control interrupt handler. | 07-03-2014 |
20140189390 | SYSTEM AND METHOD FOR CAUSING REDUCED POWER CONSUMPTION ASSOCIATED WITH THERMAL REMEDIATION - Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption. | 07-03-2014 |
20140189408 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION - Particular embodiments described herein can offer an apparatus that includes logic, the logic at least partially comprising hardware logic to receive a first notification indicating that at least one first user interaction device has become precluded; and cause, by a processor and absent intermediate operation of operating system software, disabling of at least one second user interaction device based, at least in part, on the first notification. | 07-03-2014 |
Patent application number | Description | Published |
20110138220 | METHODS AND APPARATUS TO INITIATE A BIOS RECOVERY - Methods and apparatus to initiate a basic input/output system (BIOS) recovery are disclosed herein. An example BIOS recovery module includes a memory storing one or more signatures to be detected by a detector of a BIOS implemented on a computing platform; and a connector to couple the module to a data display channel of the computing platform, wherein a BIOS recovery mechanism of the BIOS is to initiate in response to the detector detecting the one or more signatures of the module via the data display channel. | 06-09-2011 |
20130007483 | METHOD AND APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM - A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention. | 01-03-2013 |
20130132755 | POWER MANAGEMENT OF LOW POWER LINK STATES - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 05-23-2013 |
20140068135 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-06-2014 |
20140068302 | MECHANISM FOR FACILITATING FASTER SUSPEND/RESUME OPERATIONS IN COMPUTING SYSTEMS - A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state. | 03-06-2014 |
20140095908 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 04-03-2014 |
20140101470 | IDLE DURATION REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed. | 04-10-2014 |
20140223216 | POWER MANAGEMENT OF LOW POWER LINK STATES - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 08-07-2014 |
20140310543 | METHOD AND APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM - A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention. | 10-16-2014 |
20150089110 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-26-2015 |
20150095670 | REDUCING PIN COUNT REQUIREMENTS FOR IMPLEMENTATION OF INTERCONNECT IDLE STATES - Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed. | 04-02-2015 |
20150185808 | ELECTRONIC DEVICE HAVING A CONTROLLER TO ENTER A LOW POWER MODE - An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode. | 07-02-2015 |
20150257101 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 09-10-2015 |
20150277778 | VIRTUAL GENERAL-PURPOSE I/O CONTROLLER - Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed. | 10-01-2015 |
20150277935 | TECHNIQUES FOR ADAPTIVE INTERFACE SUPPORT - Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed. | 10-01-2015 |
Patent application number | Description | Published |
20080288798 | Power management of low power link states - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 11-20-2008 |
20100169684 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 07-01-2010 |
20100169685 | IDLE DURATION REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed. | 07-01-2010 |
20110276816 | POWER MANAGEMENT OF LOW POWER LINK STATES - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 11-10-2011 |
20140281622 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVING RESUME TIMES FOR ROOT PORTS AND ROOT PORT INTEGRATED ENDPOINTS - A device is determined to be in a low power state. A transition from the low power state to an active state is initiated, where a fixed minimum recovery time is defined for transitions from the low power state to the active state. A capability of the device is identified corresponding to transition of the device from the low power state to the active state, and the transition of the device from the low power state to the active state is completed based at least in part on the capability, such that the transition is to be completed prior to expiration of the fixed minimum recovery time. | 09-18-2014 |