Patent application number | Description | Published |
20110269854 | PROCESS FOR THE PRODUCTION OF METHANOL INCLUDING ONE OR MORE MEMBRANE SEPARATION TYPES - Disclosed herein is a methanol production process that includes a membrane separation step or steps. Using the process of the invention, the efficiency of methanol production from syngas is increased by reducing the compression requirements of the process and/or improving the methanol product yield. As an additional advantage, the membrane separation step generates a hydrogen-rich stream which can be sent for other uses. An additional benefit is that the process of the invention may debottleneck existing methanol plants if more syngas or carbon dioxide is available, allowing for feed of imported carbon dioxide into the synthesis loop. This is a way of sequestering carbon dioxide. | 11-03-2011 |
20140141139 | Membrane Separation Process for Controlling Gas Concentrations Within Produce Shipping or Storage Containers - Disclosed herein is a membrane separation process and system for controlling the relative concentrations of carbon dioxide, oxygen, and nitrogen within a shipping or storage container containing respiring produce. The process uses a first membrane that is selective to carbon dioxide over oxygen and nitrogen, and a second membrane that is selective to oxygen over nitrogen. | 05-22-2014 |
20140264176 | Membrane-Based Gas Separation Processes to Produce Synthesis Gas With a High CO Content - A process for producing syngas with a high content of carbon monoxide, reflected in a high CO:CO | 09-18-2014 |
20150158795 | Membrane-Based Gas Separation Processes to Separate Dehydrogenation Reaction Products - Gas separation processes are provided for separating dehydrogenation reaction products from a raw gas stream to recover hydrocarbons, specifically olefins, such as propylene and iso-butene, as well as unreacted feedstock. The processes employ a sequence of partial condensation steps, interspersed with membrane separation steps to raise the hydrocarbon dewpoint of the uncondensed gas, thereby avoiding the use of low-temperature or cryogenic conditions. | 06-11-2015 |
Patent application number | Description | Published |
20140089642 | METHODS AND SYSTEMS FOR PERFORMING A REPLAY EXECUTION - One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction. | 03-27-2014 |
20140281274 | SHARED MEMORY INTERLEAVINGS FOR INSTRUCTION ATOMICITY VIOLATIONS - A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary. | 09-18-2014 |
20140366006 | VISUALIZING RECORDED EXECUTIONS OF MULTI-THREADED SOFTWARE PROGRAMS FOR PERFORMANCE AND CORRECTNESS - A system graphically visualizes performance and/or correctness features of a recorded execution of a multi-threaded software program. The system may process chunk-based information recorded during an execution of the multi-threaded program, prepare a graphical visualization of the recorded information, and display the graphical visualization on a display in an animated fashion. The system may allow a viewer to interactively control the display of the animated graphical visualization. | 12-11-2014 |
20150074366 | APPARATUS AND METHOD FOR IMPROVED LOCK ELISION TECHNIQUES - An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section. | 03-12-2015 |
20150100741 | TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES - Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed. | 04-09-2015 |
20150186178 | Processor With Transactional Capability and Logging Circuitry To Report Transactional Operations - A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted. | 07-02-2015 |
20150277967 | Enabling Maximum Concurrency In A Hybrid Transactional Memory System - In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed. | 10-01-2015 |
20150277968 | SOFTWARE REPLAYER FOR TRANSACTIONAL MEMORY PROGRAMS - A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed. | 10-01-2015 |
Patent application number | Description | Published |
20140007054 | METHODS AND SYSTEMS TO IDENTIFY AND REPRODUCE CONCURRENCY VIOLATIONS IN MULTI-THREADED PROGRAMS USING EXPRESSIONS | 01-02-2014 |
20140189256 | PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE - A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor. | 07-03-2014 |
20140281705 | MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS - A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads. | 09-18-2014 |
20140282423 | METHODS AND APPARATUS TO MANAGE CONCURRENT PREDICATE EXPRESSIONS - Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied. | 09-18-2014 |
20150363242 | METHODS AND APPARATUS TO MANAGE CONCURRENT PREDICATE EXPRESSIONS - Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied. | 12-17-2015 |