| Patent application number | Description | Published |
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| 20090195281 | Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System - A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period. | 08-06-2009 |
| 20090310666 | ADAPTIVE EQUALIZER CIRCUIT - An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times. | 12-17-2009 |
| Patent application number | Description | Published |
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| 20090002569 | Information processing apparatus, information processing system, and controlling method of information processing apparatus - There is provided an information processing apparatus in which a great number of users can use thin clients, and in which various services such as simultaneous picture distribution are realized in an integrated manner, an information processing system, and a controlling method of the information processing apparatus. The apparatus capable of executing plural OSs includes image transmitting devices having: a GPU for receiving a drawing instruction signal of a screen output from the OS and generating an image signal of a display screen; and a communicator for transmitting the image signal of the display screen to a terminal that operates as a thin client. The devices compressively code the image signal to a digital motion picture by a coding unit as necessary. Then, the devices transmit the coded signal from the communicator. The apparatus dynamically assigns the devices to the OSs corresponding to the respective terminals via VMM. | 01-01-2009 |
| 20090190481 | ROUTE CONFIRMATION METHOD AND DEVICE - In order to preliminarily confirming whether or not a protection route to be switched over can be safely switched over during a working route being used in a unicast or multicast mode. a notification of communication confirmation/quality confirmation or multicast communication confirmation is received from a manager device is received. When the received unicast or multicast packet does not include an confirmation identifier instructed by the notification while the received unicast or multicast packet includes a destination network or multicast address instructed by the notification, the received packet is mirrored and the confirmation identifier is set in a predetermined area within a header of the packet to be transferred to a preselected protection route. When the received packet includes the destination network or multicast address and the confirmation identifier instructed by the notification, the manager device is notified of a result of the communication confirmation/quality confirmation and the packet is transferred to the protection route. | 07-30-2009 |
| 20090290500 | MEASUREMENT MANAGING APPARATUS AND COMMUNICATION SYSTEM - A test packet transmitting apparatus transmits respective test packets including different pieces of identification information to a repeating installation. The repeating installation makes a predetermined number of copies of each test packet received from the test packet transmitting apparatus to be transmitted to a test packet receiving apparatus, and determines the predetermined number of copies as a population to measure a communication quality. The test packet receiving device counts the received test packets according to each type of identification information. | 11-26-2009 |
| 20090296588 | NETWORK VERIFICATION SYSTEM - A network verification system verifies a network to which a relay apparatus relays a packet. A test management apparatus includes a condition acquiring unit to acquire verification conditions which contain an unused network address as a test target and a registering unit to register, in an address resolution table of the relay apparatus, an entry in which the unused network address contained in the acquired verification conditions is associated with a physical address of the testing apparatus. A testing apparatus includes a test packet transmitting unit to transmit, when instructed by the test management apparatus, the plurality of test packets to form a plurality of connections based on the verification conditions, a test packet receiving unit to receive the plurality of test packets and a measuring unit to measure communication qualities with respect to the respective connections of the plurality of test packets. | 12-03-2009 |
| 20100246415 | NETWORK TESTING METHOD AND SYSTEM - In order to preliminarily perform a load test or the like of an IP network, a test apparatus instructs a test packet transmitting device to transmit a test packet having a specified multicast address and instructs a test packet receiving device to receive the test packet of the multicast address. The test apparatus further instructs a first relay device to relay the test packet of the multicast address and instructs a second relay device to perform a route optimization excluding processing. The test packet receiving device requests the second relay device to transfer the test packet of the multicast address when the test packet receiving device has received the instruction to receive the test packet. | 09-30-2010 |
