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| 20090000440 | ADJUSTABLE TRIMMING ASSEMBLY - A method of trimming printed media comprises selecting printed media to be positioned on a conveyor based on predetermined delivery sequence data, positioning the printed media on the conveyor, receiving size data representative of at least one dimension of the printed media to be trimmed, and electronically controlling a trimmer based on the received size data to adjust a location at which the printed media is to be trimmed. | 01-01-2009 |
| 20100269651 | ADJUSTABLE TRIMMING ASSEMBLY - A method of trimming printed media, having a first dimension, a first edge parallel to the direction of the first dimension, and a second dimension substantially perpendicular to the first dimension, includes selecting printed media to be positioned on a conveyor based on predetermined delivery sequence data, positioning the printed media along a path on the conveyor, abutting the printed media with a stop to position the first edge of the printed media at a location along the path, receiving size data representative of the second dimension of the printed media to be trimmed, and electronically controlling at least one of the stop and a trimming device to adjust a distance between the stop and the trimming device, in a direction substantially parallel with the path, based on the received size data to adjust a location along the second dimension at which the printed media is to be trimmed. | 10-28-2010 |
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| 20080231307 | TESTING METHOD USING A SCALABLE PARAMETRIC MEASUREMENT MACRO - Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts. | 09-25-2008 |
| 20090039912 | Method of Acceptance for Semiconductor Devices - A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated. | 02-12-2009 |
| 20090106712 | RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS - A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology. | 04-23-2009 |
| 20090158444 | System and Method for Controlling Access to Addressable Integrated Circuits - A circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first listing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. A method of controlling access to addressable circuit elements is also provided. | 06-18-2009 |
| 20090164961 | Design Structure for a System For Controlling Access to Addressable Integrated Circuits - A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first thing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. | 06-25-2009 |
| 20090180584 | DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA - The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register. | 07-16-2009 |
| 20100014373 | REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT - An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed. | 01-21-2010 |
| 20120105240 | RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS - A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology. | 05-03-2012 |
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| 20110054347 | Devices for Selective Recruitment, Isolation, Activation, and/or Elimination of Various Cell Populations - Implantable devices comprise at least one or more targeting molecules that form a primary coating layer for selectively recruiting, isolating, activating, and/or eliminating any cells of interest, such as T cells, monocytes, and stem cells. The implantable devices can be utilized for selectively removing a particular subset of cells from bodily fluids of a patient. Various non-selective pharmaceutical agents and biological agents can be incorporated into the implantable devices so that cells of interest can be isolated for elimination or for activation/differentiation. Cell-type selectivity is conferred by the presence of cell-type-specific targeting molecules incorporated into the implantable device, preferably at the surface level to permit direct or indirect interaction between the cells of interest and targeting molecules of the implantable device. Related therapeutic methods for utilizing the implantable devices are also provided. These implantable devices can be manufactured as a stent, a catheter, a holding chamber, or any other device, and can be manufactured into any shape, including a conduit, a vessel, and a tubing. | 03-03-2011 |
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| 20090161858 | CONTACT SERVER FOR CALL CENTER - The present invention is a Contact server that enables customers to submit call-back requests to a call center via the Internet, or virtually any other communications technology available. A call-back to the customer can be placed via any communications technology available. In its preferred embodiment, the Contact Server enables a call-back request to be submitted by a customer directly from an HTML page on a Web site, and have that same HTML page be presented to the agent that receives the call-back request. The agent can then place a telephone call to the number provided by the customer who submitted the call-back request, and at the same time, establish a TCP/IP communications session with the customer. This TCP/IP session can proceed between the agent's Web browser and the customer's Web browser, and the visible actions performed by the agent are transferred to the customer and displayed on the customer's browser. The TCP/IP session proceeds simultaneous with the telephone call between the agent and the customer. | 06-25-2009 |
| 20100128720 | ENTERPRISE CONTACT SERVER WITH ENHANCED ROUTING FEATURES - A server may include logic configured to receive a call-back request from a customer, where the call-back request includes an identifier associated with the customer. The server may further include logic configured to identify, based on the identifier, a call center from a group of call centers having a group of agents qualified to handle the call-back request; and logic configured to forward the call-back request to the identified call center, where the call-back request causes the identified call center to select one of the group of agents to handle the call-back request. | 05-27-2010 |
| 20100232914 | METHOD AND APPARATUS FOR ROUTING WAFER PODS TO ALLOW PARALLEL PROCESSING - A method includes designating a plurality of wafers as members of a group. A first subset of the wafers is housed in a first wafer pod and a second subset of the wafers is housed in a second wafer pod. The first wafer pod is routed to a first tool, and at least a first operation is performed on the wafers in the first subset using the first tool. The second wafer pod is routed to a second tool, and the first operation is performed on the wafers in the second subset using the second tool. The wafers in the first and second subsets are consolidated following the performing of the first operation. | 09-16-2010 |
| 20100318209 | FLEXIBLE JOB PREPARATION AND CONTROL - Preparation of a wafer processing or measuring tool for a job can be initiated prior to assigning a wafer carrier to deliver wafers to the tool. The automated process may include transfer of wafers from a container, such as a bare wafer stocker, or between two tools. | 12-16-2010 |
| 20120089245 | METHOD AND APPARATUS FOR ROUTING DISPATCHING AND ROUTING RETICLES - A method includes generating a reticle transport job using a computing device. The reticle job identifies a selected reticle. A reticle pod available for transporting the reticle is autonomously identified using the computing device. The reticle transport job is updated suing the computing device with an identifier of the reticle pod. | 04-12-2012 |
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| 20110225346 | GARBAGE COLLECTION IN A STORAGE DEVICE - In general, this disclosure relates to garbage collection in a storage device. Aspects of this disclosure describe techniques to identify one or more candidate memory storage blocks that should be recycled during garbage collection. The one or more candidate memory storage blocks may be identified based at least on monitored soft metrics of the candidate memory storage blocks. During garbage collection, the identified one or more candidate memory storage blocks may be recycled to free up storage space. | 09-15-2011 |
| 20110225347 | LOGICAL BLOCK STORAGE IN A STORAGE DEVICE - In general, this disclosure relates to storage of logical blocks in a storage device. Aspects of this disclosure describe techniques to monitor the frequency of access of one or more logical blocks referenced by one or more logical block addresses. Based on the frequency of access, in non-limiting aspects of this disclosure, a controller may select one or more physical blocks of a common memory storage block. The storage device may store the logical blocks in the selected physical blocks. | 09-15-2011 |
| 20110264843 | DATA SEGREGATION IN A STORAGE DEVICE - An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization. | 10-27-2011 |
| 20120011301 | DYNAMICALLY CONTROLLING AN OPERATION EXECUTION TIME FOR A STORAGE DEVICE - In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time. | 01-12-2012 |
| 20120110239 | Causing Related Data to be Written Together to Non-Volatile, Solid State Memory - A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory. | 05-03-2012 |
| 20120124273 | Estimating Wear of Non-Volatile, Solid State Memory - Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service. | 05-17-2012 |
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| 20110185112 | Verifying Whether Metadata Identifies a Most Current Version of Stored Data in a Memory Space - Method and apparatus for verifying whether metadata identifies a most current version of data stored in a memory space. In accordance with various embodiments, a physical location within a first portion of a solid-state memory space is identified by metadata as storing a current version of user data having a selected logical address. A reverse search is performed upon a second portion of the memory space to determine whether the physical address identified by the metadata stores a stale version of the user data, or whether the physical address stores the current version. | 07-28-2011 |
| 20110185113 | Maintaining Data Integrity in a Data Storage Device - Method and apparatus for maintaining data integrity in a data storage device. In accordance with some embodiments, a memory space has a plurality of garbage collection units (GCUs) each arranged to store user data identified by logical addresses. Each GCU has a metadata region that stores metadata that correlates the logical addresses LBAs with physical addresses and a header region that stores descriptor data that identifies LBAs stored in the associated GCU. A control circuit identifies an error in the metadata from the descriptor data of a selected GCU and rebuilds the metadata to indicate a storage location of a most current version of data associated with a selected logical address. | 07-28-2011 |
| 20110231596 | Multi-Tiered Metadata Scheme for a Data Storage Array - Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group. | 09-22-2011 |
| 20110231623 | Garbage Collection Management in a Data Storage Device - Method and apparatus for handling data in a data storage device. In accordance with some embodiments, a memory space with a plurality of garbage collection units (GCUs) that are each arranged into pages of memory that store user data identified by logical addresses (LAs) and each GCU has a metadata region that stores metadata that correlates the LAs with physical addresses (PAs). A header region in each page of memory stores a bitmask and a sequence map of the LAs in each page that are used by a log manager to creates a bitmask table stored in a first cache and a hierarchical log stored in a second cache. The bitmask table and hierarchical log are used to determine when the LAs stored in the selected GCU are stale, and update the bitmask for each page in the selected GCU after the stale data has been erased. | 09-22-2011 |
| 20110258380 | FAULT TOLERANT STORAGE CONSERVING MEMORY WRITES TO HOST WRITES - A data storage apparatus and associated method involving a memory with a plurality of storage elements defining an associated set of stored data, and memory control logic that, responsive to a request to store first data in a first storage element of the plurality of storage elements, computes without storing to any of the plurality of storage elements first redundancy data for the associated set of stored data inclusive of the first data. | 10-20-2011 |
| 20110302474 | Ensuring a Most Recent Version of Data is Recovered From a Memory - Method and apparatus for ensuring a most recent version of data is retrieved from a memory, such as a non-volatile flash memory array. In accordance with various embodiments, a controller is adapted to sequentially store different versions of an addressable data block having a selected logical address in different locations within a memory. The controller assigns a revision indication value to each said version, with at least two of said stored versions concurrently sharing the same revision indication value. In some embodiments, the revision indication value constitutes a repeating cyclical sequence count that is appended to each block, or logically combined with a code value and stored with each block. The total number of counts in the sequence is less than the total number of versions resident in the memory. | 12-08-2011 |
| 20110302477 | Data Hardening to Compensate for Loss of Data Retention Characteristics in a Non-Volatile Memory - Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations. | 12-08-2011 |
| 20120072639 | Selection of Units for Garbage Collection in Flash Memory - A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest. | 03-22-2012 |
| 20120102259 | Predictive Read Channel Configuration - The read channel of a solid state non-volatile memory may be configured to compensate for shifts in the threshold voltages of memory cells of the memory. A log of write time information and write temperature information from one or more write operations is stored in a data unit header. The read channel configuration, which may include reference voltages used for the read operation, is determined using the write time information and the write temperature information. Memory cells of the data unit are read using the configured read channel. A historical profile spanning multiple write operations may also be developed and used to configure the read channel. | 04-26-2012 |
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| 20080246789 | INKJET PRINTER HAVING SWITCHED FIRING OF ADJACENT NOZZLES APPLYING COMMON COLOR - A printing system includes a printhead having adjacent inkjet nozzles for dispensing a common colored ink and a controller adapted to direct firing of the adjacent inkjet nozzles so that adjacent local areas using the common colored ink are printed on a printing medium with alternate firings of the adjacent inkjet nozzles. | 10-09-2008 |
| 20080246801 | Operating Mechanism for an Inkjet Printer - A printer system includes a print head assembly that ejects a printing solution from a fixed position during a print period and a conveying mechanism operable to convey an operations assembly. The operations assembly executes servicing functions on the print head assembly during a non-print period. Furthermore, the print head assembly remains in the fixed position during the non-print period and the operations assembly provides support for a print medium during the print period. | 10-09-2008 |
| 20080309993 | EXECUTING OPERATIONS IN CONNECTION WITH ONE OR MORE IMAGES WITH A PRINTER - Methods and systems are provided to facilitate a printer to execute one or more operations in connection with one or more images are described herein. The methods may include methods that may, at least in part, be implemented at a printer including tracking one or more locations of a scan device with respect to a sheet having a first one or more pictures associated with one or more corresponding images, wherein the tracking is based, at least in part, on electronic data provided by the scan device. The printer may then based at least in part on the tracking, execute at least one operation in connection with all or a selected subset of the one or more corresponding images. | 12-18-2008 |
| 20100277534 | MECHANICAL DITHERING OF PRINTING MECHANISMS - A system comprises a control module that communicates with a printhead having nozzles, that detects a malfunctioning nozzle, and that generates control signals when the malfunctioning nozzle is detected. A vibration generator selectively vibrates the printhead along a first axis of a print medium based on the control signals. The first axis is selected from a group consisting of parallel and perpendicular to a second axis of motion of the print medium. | 11-04-2010 |
| 20110075183 | PRINT AND SCAN SHARING PAPER PICK AND PAPER MOTION CONTROL IN A MULTI-FUNCTION PRINTER - A multi-function printer having a compact size and portable configuration while providing printing, scanning and copying functionalities is disclosed herein. The multi-function printer includes a printer assembly and a scanner assembly configured to cooperatively utilize the same pick and paper movement systems along a common feed or paper path to perform these printing, scanning and copying functions. Thus, the disclosed multi-function printer may require a less complex paper movement and control system which, in turn, reduces the printer's overall weight while increasing its flexibility and/or portability. | 03-31-2011 |
