Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees

Gosalia, US

Anuj B. Gosalia, Redmond, WA US

Patent application number	Description	Published
20080301687	SYSTEMS AND METHODS FOR ENHANCING PERFORMANCE OF A COPROCESSOR - Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.	12-04-2008
20100122259	Multithreaded kernel for graphics processing unit - Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.	05-13-2010

Anuj Bharat Gosalia, Redmond, WA US

Patent application number	Description	Published
20090217252	OPTIMIZING COMPILER TRANSFORMS FOR A HIGH LEVEL SHADER LANGUAGE - A high level shader language compiler incorporates transforms to optimize shader code for graphics processing hardware. An instruction reordering transform determines instruction encapsulations of dependent instructions that reduce concurrent register usage by the shader. A phase pulling transform re-organizes the shader's instructions into phases that reduce a measure of depth of texture loads. A register assigning transform assigns registers to lower register usage by the shader.	08-27-2009

Ashit Gosalia, Bellevue, WA US

Patent application number	Description	Published
20110231403	SCALABLE INDEX BUILD TECHNIQUES FOR COLUMN STORES - Architecture that includes an index creation algorithm that utilizes available resources and dynamically adjusts to successfully scale with increased resources and be able to do so for any data distribution. The resources can be processing resources, memory, and/or input/output, for example. A finer level of granularity, called a segment, is utilized to process tuples in a partition while creating an index. The segment also aligns with compression techniques for the index. By choosing an appropriate size for a segment and using load balancing the overall time for index creation can be reduced. Each segment can then be processed by a single thread thereby limiting segment skew. Skew is further limited by breaking down the work done by a thread into parallelizable stages.	09-22-2011

Ashit R. Gosalia, Bellevue, WA US

Patent application number	Description	Published
20090207521	TECHNIQUES FOR IMPROVING PARALLEL SCAN OPERATIONS - Various technologies and techniques are disclosed for improving performance of parallel scans. Disk head randomization that occurs when performing a parallel scan is minimized by assigning a worker entity to each disk involved in the parallel scan, and by ensuring data is only accessed on a respective disk by the worker entity assigned to the disk. A parallel scan can be performed that is NUMA aware by ensuring a particular sub-set of data is resident in the same memory node during each parallel scan, and by ensuring the particular sub-set of data is processed by a worker entity assigned to a node in which the sub-set of data is resident. A process for performing a parallel scan involves breaking up work into sub-sets, assigning work to each worker entity that corresponds to a respective disk, and having the worker entities process the assigned work to complete the parallel scan.	08-20-2009

Rishi H. Gosalia, Austin, TX US

Patent application number	Description	Published
20090288073	Edit Time Analyzer in a Loosely Typed Textual Language - Analyzing code written in a loosely typed language. User input specifying code for a script may be received. The specified code may be analyzed. More specifically, one or more code portions referenced by the specified code may be determined. Properties of symbols of the specified code and the one or more code portions may also be determined. Additionally, the specified code may be analyzed using the determined properties to determine errors in the specified code. Accordingly, one or more errors may be graphically indicated based on said analyzing. Receiving the user input, analyzing the specified code, and graphically indicating the one or more errors may be performed at edit time.	11-19-2009
20100057417	Generating a Hardware Description for a Programmable Hardware Element Based on a Graphical Program Including Multiple Physical Domains - Generating a hardware description for a programmable hardware element based on a graphical program including multiple physical domains. A graphical program may be received which includes a first portion of a first physical domain for simulating a first portion of a physical system. The graphical program may include a second portion of a second physical domain for simulating a second portion of the physical system. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to simulate the physical system.	03-04-2010
20100058289	Generating a Hardware Description for a Programmable Hardware Element Based on a Graphical Program Including Multiple Models of Computation - Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program.	03-04-2010
20100325611	Providing Target Specific Information for Textual Code at Edit Time - Providing target specific information for textual code at edit time. Input specifying textual code or the textual code itself may be received. The textual code may be specified for a target device. The textual code may be analyzed to determine information regarding execution of the textual code on the target device. The information may regard at least one statement of the textual code. The information may be provided for display. The analysis and provision of information may be performed at edit time.	12-23-2010
20100325617	Compiling a Graphical Program Having a Textual Language Program Portion for a Real Time Target - Compiling a graphical program including a textual program portion for execution on a real time target. The graphical program may be created on a display or stored in a memory medium. The graphical program may include a plurality of connected nodes which visually indicate functionality of the graphical program. The graphical program may include at least one node which corresponds to a textual language program portion. The textual language program portion may be written or specified in a dynamically typed programming language. The graphical program may be compiled for deployment on the real time target. Compiling the graphical program may include compiling the plurality of connected nodes and the textual language program portion for deterministic real time execution on the real time target.	12-23-2010
20110078662	Debugging a Graphical Program Deployed on a Programmable Hardware Element - Debugging a graphical program deployed on a programmable hardware element. The graphical program may be received. The graphical program may include a plurality of nodes and connections between the nodes which visually represents functionality of the graphical program. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be deployed to the programmable hardware element and the programmable hardware element may be executed. The graphical program may be displayed on a display of a host computer system that is coupled to the programmable hardware element. Debugging information may be received from the programmable hardware element during said executing. The debugging information from the programmable hardware element may be displayed in the graphical program displayed on the display. The displayed debugging information may be used to debug the hardware implementation of the graphical program.	03-31-2011