Patent application number | Description | Published |
20080258210 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material. | 10-23-2008 |
20080290469 | Edge Seal For a Semiconductor Device and Method Therefor - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 11-27-2008 |
20090042366 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 02-12-2009 |
20090045440 | METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate. | 02-19-2009 |
20090079001 | MULTI-CHANNEL ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode. | 03-26-2009 |
20090079032 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 03-26-2009 |
20090096021 | SEMICONDUCTOR DEVICE HAVING DEEP TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers. | 04-16-2009 |
20090108342 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate. | 04-30-2009 |
20090108343 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. Field plate trenches extend into the semiconductor material and field plates are formed in the field plate trenches. A gate trench is formed between two adjacent field plate trenches and another gate trench is formed adjacent one of the field plate trenches. Gate structures are formed in the gate trenches, wherein each gate structure includes a gate oxide and a gate conductor. A conductor electrically couples the field plates together. | 04-30-2009 |
20090267204 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
20090269912 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 03-11-2010 |
20100072573 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 03-25-2010 |
20100120227 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 05-13-2010 |
20100120230 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 05-13-2010 |
20100123187 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE AND METHOD - In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion. | 05-20-2010 |
20100140694 | SEMICONDUCTOR DEVICE HAVING SUB-SURFACE TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers. | 06-10-2010 |
20100184272 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 07-22-2010 |
20100187642 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region. | 07-29-2010 |
20100187696 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a contact landing pad and a method for manufacturing the semiconductor component. A trench having sidewalls is formed in a semiconductor material and a dielectric material is formed on the sidewalls of the trench. An electrically conductive material is formed on the sidewalls and fills the trench. A multi-layer dielectric structure is formed over the electrically conductive material in the trench, where the multi-layer dielectric material is comprised of a dielectric material of one type sandwiched between dielectric materials of a different type such that an etch rate of the middle layer of dielectric material is different from those of the outer layers of dielectric material. Portions of the middle layer of dielectric material are removed and replaced with electrically conductive material that, in combination with portions of the electrically conductive material in the trench, form a contact landing pad. | 07-29-2010 |
20100219531 | METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR CONTACT AND STRUCTURE THEREFOR - In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides. | 09-02-2010 |
20110136309 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions. | 06-09-2011 |
20110136310 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers. | 06-09-2011 |
20110175209 | METHOD OF FORMING AN EM PROTECTED SEMICONDUCTOR DIE - In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls. | 07-21-2011 |
20110175225 | METHOD OF FORMING AN EM PROTECTED SEMICONDUCTOR DIE - In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls. | 07-21-2011 |
20110175242 | METHOD OF FORMING A SEMICONDUCTOR DIE - In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer. | 07-21-2011 |
20110177675 | METHOD OF FORMING A SEMICONDUCTOR DIE - In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer. | 07-21-2011 |
20110233635 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 09-29-2011 |
20110244657 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 10-06-2011 |
20120112278 | ELECTRONIC DEVICE INCLUDING A WELL REGION - An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region. | 05-10-2012 |
20120142171 | METHOD OF FORMING A HIGH CAPACITANCE DIODE - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 06-07-2012 |
20120244681 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 09-27-2012 |
20120248548 | ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT WITH TRANSISTORS COUPLED TO EACH OTHER - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 10-04-2012 |
20120276703 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. | 11-01-2012 |
20120292732 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 11-22-2012 |
20120313161 | SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD - In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. | 12-13-2012 |
20120319188 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 12-20-2012 |
20120326227 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE - In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness. | 12-27-2012 |
20130043526 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE WITH SOURCE-SUBSTRATE CONNECTION AND STRUCTURE - In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate. | 02-21-2013 |
20130153987 | ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME - An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench. | 06-20-2013 |
20130153988 | ELECTRONIC DEVICE INCLUDING A TRENCH WITH A FACET AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator. | 06-20-2013 |
20130221436 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device. | 08-29-2013 |
20130248982 | SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD - In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. | 09-26-2013 |
20130277807 | ELECTRONIC DEVICE INCLUDING A FEATURE IN AN OPENING - A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows. | 10-24-2013 |
20130288449 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 10-31-2013 |
20130299996 | METHOD OF MAKING AN ELECTRODE CONTACT STRUCTURE AND STRUCTURE THEREFOR - In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion. | 11-14-2013 |
20130302958 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer. | 11-14-2013 |
20130320428 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 12-05-2013 |
20140048917 | EM PROTECTED SEMICONDUCTOR DIE - In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls. | 02-20-2014 |
20140070375 | ELECTRONIC DEVICE INCLUDING A VIA AND A CONDUCTIVE STRUCTURE, A PROCESS OF FORMING THE SAME, AND AN INTERPOSER - An electronic device can include a substrate including a first region having a first thickness, and a second region having a second thickness different from the first thickness. The electronic device can include a via within the first region. The electronic device can include a conductive structure adjacent to the first region and connected to the via, wherein a combined thickness of the first thickness and a thickness of the conductive structure is thicker than the second thickness. In another embodiment, an interposer may have a similar structure, with laterally offset conductive structures that allow for lateral routing of electronic signals. A process of forming an electronic device can include forming a via and removing a portion of the substrate. The process can include forming a conductive structure connected to the via, wherein the conductive structure is adjacent to a region where the portion of the substrate has been removed. | 03-13-2014 |
20140087542 | SEMICONDUCTOR DIE SINGULATION APPARATUS AND METHOD - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 03-27-2014 |
20140091399 | ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A VERTICLE CONDUCTIVE STRUCTURE - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 04-03-2014 |
20140127880 | SEMICONDUCTOR DIE SINGULATION METHOD AND APPARATUS - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. | 05-08-2014 |
20140127885 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. Heat is applied to the first carrier substrate while the localized pressure is applied. | 05-08-2014 |
20140134828 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape. | 05-15-2014 |
20140145256 | ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH - An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench. | 05-29-2014 |
20140197483 | TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner. | 07-17-2014 |
20140235034 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 08-21-2014 |
20140242780 | Method and Apparatus for Plasma Dicing a Semi-Conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising: providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate on a carrier support to form a work piece; providing an intermediate ring interposed between the substrate and the frame; loading the work piece onto the work piece support; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 08-28-2014 |
20140252430 | Electronic Device Including a Dielectric Layer Having a Non-Uniform Thickness and a Process of Forming The Same - An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed. | 09-11-2014 |
20140252473 | Electronic Device Including a Vertical Conductive Structure and a Process of Forming the Same - An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped region and a vertical conductive region, wherein the vertical conductive region is electrically connected to the horizontally-oriented doped region and the buried conductive region. The electronic device can still further include an insulating layer overlying the horizontally-oriented doped region, and a first conductive electrode overlying the insulating layer and the horizontally-oriented doped region, wherein a portion of the vertical conductive region does not underlie the first conductive electrode. The electronic device can include a Schottky contact that allows for a Schottky diode to be connected in parallel with a transistor. Processes of forming an electronic device allow a vertical conductive region to be formed after a conductive electrode, a gate electrode, a source region, or both. | 09-11-2014 |
20140252484 | Electronic Device Including a Schottky Contact - An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator. | 09-11-2014 |
20140264452 | METHOD OF FORMING A HEMT SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors. | 09-18-2014 |
20140264523 | ELECTRONIC DEVICE INCLUDING A CAPACITOR STRUCTURE AND A PROCESS OF FORMING THE SAME - An electronic device can include a capacitor structure. In an embodiment, the electronic device can include a buried conductive region, a semiconductor layer having a primary surface, a horizontally-oriented doped region adjacent to the primary surface, an insulating layer overlying the horizontally-oriented doped region, and a conductive electrode overlying the insulating layer. The capacitor structure can include a first capacitor electrode including a vertical conductive region electrically connected to the horizontally-oriented doped region and the buried conductive region. The capacitor structure can further include a capacitor dielectric layer and a second capacitor electrode within a trench. The capacitor structure can be spaced apart from the conductive electrode. In another embodiment, an electronic device can include a first transistor, a trench capacitor structure, and a second transistor, wherein the first transistor is coupled to the trench capacitor structure, and the second transistor does not have a corresponding trench capacitor structure. | 09-18-2014 |
20140264565 | METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor. | 09-18-2014 |
20140264574 | ELECTRONIC DEVICE INCLUDING VERTICAL CONDUCTIVE REGIONS AND A PROCESS OF FORMING THE SAME - An electronic device can include different vertical conductive structures that can be formed at different times. The vertical conductive structures can have the same or different shapes. In an embodiment, an insulating spacer can be used to help electrically insulate a particular vertical conductive structure from another part of the workpiece, and an insulating spacer may not be used to electrically isolate a different vertical conductive structure. The vertical conductive structures can be tailored for particular electrical considerations or to a process flow when formation of other electronic components may also be formed within either or both of the particular vertical conductive structures. | 09-18-2014 |
20140319644 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 10-30-2014 |
20150027290 | SEMICONDUCTOR DIE SINGULATION METHODS - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 01-29-2015 |
20150028414 | INSULATED GATE SEMICONDUCTOR DEVICE STRUCTURE - In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness. | 01-29-2015 |
20150054068 | SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD - In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. | 02-26-2015 |
20150069610 | ELECTRODE CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE - In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion. | 03-12-2015 |