| Patent application number | Description | Published |
|---|
| 20080258210 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material. | 10-23-2008 |
| 20080290469 | Edge Seal For a Semiconductor Device and Method Therefor - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 11-27-2008 |
| 20090042366 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 02-12-2009 |
| 20090045440 | METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate. | 02-19-2009 |
| 20090079001 | MULTI-CHANNEL ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode. | 03-26-2009 |
| 20090079032 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 03-26-2009 |
| 20090096021 | SEMICONDUCTOR DEVICE HAVING DEEP TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers. | 04-16-2009 |
| 20090108342 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate. | 04-30-2009 |
| 20090108343 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. Field plate trenches extend into the semiconductor material and field plates are formed in the field plate trenches. A gate trench is formed between two adjacent field plate trenches and another gate trench is formed adjacent one of the field plate trenches. Gate structures are formed in the gate trenches, wherein each gate structure includes a gate oxide and a gate conductor. A conductor electrically couples the field plates together. | 04-30-2009 |
| 20090267204 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
| 20090269912 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
| 20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 03-11-2010 |
| 20100072573 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 03-25-2010 |
| 20100120227 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 05-13-2010 |
| 20100120230 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 05-13-2010 |
| 20100123187 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE AND METHOD - In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion. | 05-20-2010 |
| 20100140694 | SEMICONDUCTOR DEVICE HAVING SUB-SURFACE TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers. | 06-10-2010 |
| 20100184272 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 07-22-2010 |
| 20100187642 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region. | 07-29-2010 |
| 20100187696 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a contact landing pad and a method for manufacturing the semiconductor component. A trench having sidewalls is formed in a semiconductor material and a dielectric material is formed on the sidewalls of the trench. An electrically conductive material is formed on the sidewalls and fills the trench. A multi-layer dielectric structure is formed over the electrically conductive material in the trench, where the multi-layer dielectric material is comprised of a dielectric material of one type sandwiched between dielectric materials of a different type such that an etch rate of the middle layer of dielectric material is different from those of the outer layers of dielectric material. Portions of the middle layer of dielectric material are removed and replaced with electrically conductive material that, in combination with portions of the electrically conductive material in the trench, form a contact landing pad. | 07-29-2010 |
| 20100219531 | METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR CONTACT AND STRUCTURE THEREFOR - In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides. | 09-02-2010 |
| 20110136309 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions. | 06-09-2011 |
| 20110136310 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers. | 06-09-2011 |
