Patent application number | Description | Published |
20090287532 | PROVIDING AN ELECTRONIC MARKETPLACE TO FACILITATE HUMAN PERFORMANCE OF PROGRAMMATICALLY SUBMITTED TASKS - A method, system, and computer-readable medium is described for facilitating interactions between task requesters who have tasks that are available to be performed and task performers who are available to perform tasks. In some situations, the tasks to be performed are human performance tasks that use cognitive and other mental skills of human task performers, such as to employ judgment, perception and/or reasoning skills of the human task performers. In addition, in some situations the available tasks are submitted by human task requesters via application programs that programmatically invoke one or more application program interfaces of an electronic marketplace in order to request that the tasks be performed and to receive corresponding results of task performance in a programmatic manner, so that an ensemble of unrelated human agents can interact with the electronic marketplace to collectively perform a wide variety and large number of tasks. | 11-19-2009 |
20130081036 | PROVIDING AN ELECTRONIC MARKETPLACE TO FACILITATE HUMAN PERFORMANCE OF PROGRAMMATICALLY SUBMITTED TASKS - A method, system, and computer-readable medium is described for facilitating interactions between task requesters who have tasks that are available to be performed and task performers who are available to perform tasks. In some situations, the tasks to be performed are human performance tasks that use cognitive and other mental skills of human task performers, such as to employ judgment, perception and/or reasoning skills of the human task performers. In addition, in some situations the available tasks are submitted by human task requesters via application programs that programmatically invoke one or more application program interfaces of an electronic marketplace in order to request that the tasks be performed and to receive corresponding results of task performance in a programmatic manner, so that an ensemble of unrelated human agents can interact with the electronic marketplace to collectively perform a wide variety and large number of tasks. | 03-28-2013 |
Patent application number | Description | Published |
20080204052 | INTEGRATED CIRCUIT SYSTEM WITH MOS DEVICE - An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof. | 08-28-2008 |
20080286887 | Method for adjusting a transistor model for increased circuit simulation accuracy - According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model. | 11-20-2008 |
20090094013 | TWO-STEP SIMULATION METHODOLOGY FOR AGING SIMULATIONS - The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation. | 04-09-2009 |
20090101976 | BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT - A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region. | 04-23-2009 |
20100144106 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor. | 06-10-2010 |
20110086484 | BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT - A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region. | 04-14-2011 |
20110204429 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor. | 08-25-2011 |
20130117001 | Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device - A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus. | 05-09-2013 |
20130117002 | Method and Apparatus for Simulating Junction Capacitance of a Tucked Transistor Device - A tucked transistor device has a diffusion region defined in a semiconductor layer, a switching gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode. A method includes receiving a netlist having an entry for the tucked transistor device in a computing apparatus, the entry defining parameters associated with the switching gate electrode and the diffusion region, receiving a device parameter file including at least a gate bounded junction capacitance parameter that includes a junction capacitance bounded by the switching gate electrode modified to include a contribution of the floating gate electrode to a gate bounded junction capacitance of the tucked transistor device. Operation of the tucked transistor device is simulated in the computing apparatus using a transistor device model and the netlist. | 05-09-2013 |