Patent application number | Description | Published |
20100005277 | Communicating Between Multiple Threads In A Processor - In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed. | 01-07-2010 |
20110197195 | THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT - A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads. | 08-11-2011 |
20120047398 | Detecting Soft Errors Via Selective Re-Execution - In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed. | 02-23-2012 |
20130283277 | THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT - A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads. | 10-24-2013 |
Patent application number | Description | Published |
20110072283 | Microarchitecture Controller For Thin-Film Thermoelectric Cooling - A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control. | 03-24-2011 |
20110197195 | THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT - A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads. | 08-11-2011 |
20120324266 | Microarchitecture Controller For Thin-Film Thermoelectric Cooling - A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control. | 12-20-2012 |
20130283277 | THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT - A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads. | 10-24-2013 |