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Gomyo, JP
Akiko Gomyo, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090142018 | Method for incidence of light into a photonic crystal optical waveguide - Disclosed in a method and a device in which a wave number of light in the waveguide mode of a photonic crystal optical waveguide is matched with that of the incident light, or a intensity ratio of electric field to magnetic field of the light in the waveguide mode of the photonic crystal optical waveguide is matched with that of the incident light, and furthermore, in addition to the method above, the distribution of light intensity on the incident end surface in the waveguide mode of the photonic crystal optical waveguide is matched with that of the incident light. A photonic crystal optical waveguide and channel optical waveguide are joined together, and the structure of the channel optical waveguide is wedge shaped in the joint section. | 06-04-2009 |
| 20100074571 | OPTICAL WAVEGUIDE ELEMENT AND METHOD FOR POLARIZATION SPLITTING - Disclosed is an optical waveguide element that includes first and second optical waveguides ( | 03-25-2010 |
Kazumasa Gomyo, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090113027 | PERSONAL NETWORK MANAGEMENT METHOD AND PERSONAL NETWORK MANAGEMENT APPARATUS - A personal network management method wherein if an access request is received from a communication terminal exterior to a personal network and the association of communication terminal information of the access request with the corresponding terminal in the personal network has not been registered yet, then the registration as to whether the connection to the communication terminal is permissible can be dynamically performed, and wherein the procedure of a registration from a communication terminal exterior to a personal network is facilitated, and an access into the personal network also can be performed. In a network system ( | 04-30-2009 |
| 20110007009 | PORTABLE TERMINAL DEVICE, DISPLAY CONTROL METHOD, AND DISPLAY CONTROL PROGRAM - There is provided a portable terminal device that enables a user to operate all buttons to be operated by moving only one finger of one hand carrying the terminal when operating the terminal equipped with both a touch panel and a stationary operation section and that exhibits superior operability. The portable terminal device has enclosures | 01-13-2011 |
| 20110151938 | PORTABLE TERMINAL DEVICE AND INPUT OPERATION METHOD AND DISPLAY CONTROL METHOD OF THE PORTABLE TERMINAL DEVICE - A purpose of the invention is to provide a portable phone capable of allowing a user to comfortably use an application when the portable phone is placed on a mounting object such as a desk, and to provide an input operation method and a display control method of the portable phone. A horizontal state of a lower housing ( | 06-23-2011 |
Kazumasa Gomyo, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100115308 | COMMUNICATION DEVICE AND POWER SUPPLY METHOD - Provided is a communication device capable of efficiently performing a power supply control when reducing power consumption by reducing the time during which the power is supplied. In the device, a CPU power saving control unit ( | 05-06-2010 |
| 20100211777 | WIRELESS TERMINAL DEVICE, WIRELESS CONNECTION METHOD, AND PROGRAM - A wireless terminal device which can be easily connected with an access point with a simple procedure and with no expertise, a wireless connection method and a program are provided. In a wireless terminal device ( | 08-19-2010 |
| 20100217881 | WIRELESS TERMINAL DEVICE, WIRELESS CONNECTION METHOD, AND PROGRAM - A wireless terminal device which can be connected to a wireless LAN service to which the terminal can be connected without regard to the identifier for specifying a wireless LAN service, a wireless connection method, and a program are provided. A wireless terminal device ( | 08-26-2010 |
| 20100296495 | WIRELESS LAN COMMUNICATION DEVICE AND BEACON TRANSMITTING METHOD - A wireless LAN communication device is provided for making it possible to set beacons including DTIM information elements not to be synchronous in the case that the timing for generating the beacons including DTIM information elements is the same among access points, so that it is avoidable that only a terminal device under a specific access point among access points using the same channel is subjected to a delay and jitters, while anxiety about mutual interference of the terminal devices is removed in the case of broadcast and multicast service, so that a fair broadcast and multicast service can be received. In the device, a wireless LAN control unit ( | 11-25-2010 |
Makoto Gomyo, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090231501 | METHOD FOR DRIVING LIQUID CRYSTAL DEVICE AND DRIVING APPARATUS FOR THE LIQUID CRYSTAL DEVICE - Sequentially performed are (1) an entire liquid crystal layer is initialized into a focal conic state, (2) an image is written onto the liquid crystal device by scanning with selecting exposure or non-exposure while applying a voltage that does not exceed a threshold value for a state change from the focal conic state to a homeotropic state during the non-exposure but exceeds the threshold value during the exposure and that causes the focal conic state and the homeotropic state to be bi-stable after the exposure, and (3) the application of the voltage is stopped to change a state of a portion, of which the state has changed to the homeotropic state, to the planer state. In (2), an electric field energy applied to an exposure portion of the liquid crystal layer is controlled to gradually increase from a start to an end of the series of scanning actions. | 09-17-2009 |
Masayuki Gomyo, Hadano JP
| Patent application number | Description | Published |
|---|---|---|
| 20110246706 | DISK ARRAY CONFIGURATION PROGRAM, COMPUTER, AND COMPUTER SYSTEM - To improve the data input/output performance of a disk array with a hybrid configuration of flash memory and HDDs. A computer that executes a disk array configuration program in accordance with the present invention, when relocating a file from a hard disk to flash memory, stores the file in cache memory without immediately writing the file to the flash memory if the file size is smaller than the block size of the flash memory. | 10-06-2011 |
Norihito Gomyo, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100088544 | ARITHMETIC DEVICE FOR CONCURRENTLY PROCESSING A PLURALITY OF THREADS - A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device | 04-08-2010 |
| 20100095306 | ARITHMETIC DEVICE - An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device | 04-15-2010 |
| 20110161764 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING PROCESSOR - A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal. | 06-30-2011 |
| 20110314262 | PREFETCH REQUEST CIRCUIT - A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows. | 12-22-2011 |
Toshio Gomyo, Nagano-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20120133056 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS AND SEMICONDUCTOR DEVICE FABRICATING METHOD - There is provided a semiconductor device which includes a primary semiconductor chip | 05-31-2012 |
Toshio Gomyo, Nagano JP
| Patent application number | Description | Published |
|---|---|---|
| 20110039370 | Electronic parts packaging structure and method of manufacturing the same - In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction. | 02-17-2011 |