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Goller, DE
Bernd Goller, Otterfing DE
| Patent application number | Description | Published |
|---|---|---|
| 20090212404 | LEADFRAME HAVING MOLD LOCK VENT - A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge. | 08-27-2009 |
| 20100227436 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE WITH MOLD LOCK OPENING - A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer. | 09-09-2010 |
Bernhard Goller, Penzberg DE
| Patent application number | Description | Published |
|---|---|---|
| 20090143375 | Tricyclic Lactam Derivatives, Their Manufacture and Use as Pharmaceutical Agents - Objects of the present invention are the compounds of formula I | 06-04-2009 |
| 20090221599 | PHTHALAZINONE PYRAZOLE DERIVATIVES, THEIR MANUFACTURE AND USE AS PHARMACEUTICAL AGENTS - Objects of the present invention are the compounds of formula I | 09-03-2009 |
| 20090291968 | SUBSTITUTED INDAZOLE DERIVATIVES, THEIR MANUFACTURE AND USE AS PHARMACEUTICAL AGENTS - Objects of the present invention are the compounds of formula I | 11-26-2009 |
Daniel Goller, Reutlingen, Fed.rep DE
| Patent application number | Description | Published |
|---|---|---|
| 20090121000 | Envelope - An envelope of at least two parallel layers ( | 05-14-2009 |
Hans-Peter Goller, Remscheid DE
| Patent application number | Description | Published |
|---|---|---|
| 20090056076 | Pivot Device - A pivot device has a first hinge part and a second hinge part pivotably connected to the first hinge part about a pivot axis. A blocking device secures the first and second hinge parts in a pivoted position relative to one another against backward and forward pivoting out of the pivoted position. The blocking device has first and second friction surfaces that, when pivoting the first and second hinge parts relative to one another, glide across one another and move axially relative to one another in an axial direction of the pivot axis as a pivot angle between the first and second hinge parts increases. | 03-05-2009 |
Joerg Goller, Zweikirchen DE
| Patent application number | Description | Published |
|---|---|---|
| 20080265967 | INTEGRATED CIRCUIT FOR CLOCK GENERATION FOR MEMORY DEVICES - A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK | 10-30-2008 |
Klaus Goller, Regensburg DE
| Patent application number | Description | Published |
|---|---|---|
| 20080303169 | Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same - An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via. | 12-11-2008 |
| 20090148996 | METHOD OF MAKING A SEMICONDUCTOR ELEMENT - A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode. | 06-11-2009 |
| 20090263964 | INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased | 10-22-2009 |
| 20100309606 | Capacitor Arrangement And Method For Making Same - One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level. | 12-09-2010 |
| 20100320613 | INTEGRATED CIRCUIT ARRANGEMENT WITH AN AUXILIARY INDENTATION, PARTICULARLY WITH ALIGNING MARKS - An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement. | 12-23-2010 |
Mathias Goller, Pfarrkirchen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100004923 | Method and an apparatus for clustering process models - The invention relates to an apparatus for clustering process models each consisting of model elements comprising a text phrase which describes in a natural language a process activity according to a process modeling language grammar and a natural language grammar, wherein said apparatus comprises a process object ontology memory for storing a process object ontology, a distance calculation unit for calculating a distance matrix employing said processing modeling language grammar and said natural language grammar, wherein said distance matrix consists of distances each indicating a dissimilarity of a pair of said process models, and a clustering unit which partitions said process models into a set of clusters based on said calculated distance matrix. | 01-07-2010 |
Michael Goller, Muensingen-Rietheim DE
| Patent application number | Description | Published |
|---|---|---|
| 20110030848 | METHOD FOR PROCESSING WORKPIECES - A method for machining workpieces in a machine tool, according to which the workpiece ( | 02-10-2011 |