Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Goh, MY
Chee How Goh, Ipoh MY
| Patent application number | Description | Published |
|---|---|---|
| 20080301397 | Method and arrangements for utilizing NAND memory - A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag. | 12-04-2008 |
Denis Chuan Hu Goh, Gelugor MY
| Patent application number | Description | Published |
|---|---|---|
| 20100251201 | INTERACTIVE SIMPLIFICATION OF SCHEMATIC DIAGRAM OF INTEGRATED CIRCUIT DESIGN - The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands. The content of selected entities can be changed by using the drag-and-drop technique for certain operations including moving nodes into, removing nodes from, and adding nodes into an entity. | 09-30-2010 |
Kim Fah Goh, Melaka MY
| Patent application number | Description | Published |
|---|---|---|
| 20100108313 | COILED TUBING CONVEYED COMBINED INFLOW AND OUTFLOW CONTROL DEVICES - Methods and systems of hydrocarbon production where wellbore stimulation and production is achieved in a single wellbore run-in, and inflow control devices are installed in an existing wellbore completion. A coiled tubing string is conveyed into a substantially horizontal portion of a wellbore, where the coiled tubing string has a production tubular configured to execute both stimulation and recovery operations. The production tubular can include an inflow control device to be installed in an existing wellbore. | 05-06-2010 |
Koh Hoo Goh, Muar Johor MY
| Patent application number | Description | Published |
|---|---|---|
| 20090250807 | Electronic Component and Method for its Production - An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s). | 10-08-2009 |
Kok Siang Goh, Perak MY
| Patent application number | Description | Published |
|---|---|---|
| 20090026594 | Thin Plastic Leadless Package with Exposed Metal Die Paddle - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 01-29-2009 |
Ling How Goh, Pulau Pinang MY
| Patent application number | Description | Published |
|---|---|---|
| 20080301615 | Focused ion beam defining process enhancement - Embodiments employ a method to define points on selected nets in a netlist for a focused ion beam (FIB) to create open circuits. A selected net is partitioned into a set of sub-segments, and after considering all metal layers at and above that of the selected net, a subset of the set of sub-segments is formed as those sub-segments having minimum distances from the considered metal layers greater than some threshold. All contiguous sub-segments in the subset of the set of sub-segments are grouped into groups. The midpoints of such groups, and any isolated sub-segments, are possible candidate for FIB points. For some embodiments, the midpoint of the longest (or one of the longest) groups of sub-segments is chosen as the FIB point for the selected net. Other embodiments are described and claimed. | 12-04-2008 |
Soon Lock Goh, Bukit Platu Mutiara MY
| Patent application number | Description | Published |
|---|---|---|
| 20110309493 | Electronic Device Package Locking System and Method - Device and method for an electronic device package is disclosed. The electronic device package includes a first pad, a second pad and an encapsulation surrounding the first and second pad, wherein the encapsulation includes a first opening underneath the first pad and a second opening underneath the second pad. A first bump is arranged in the first opening and a second bump is arranged in the second opening, wherein the encapsulation mechanically locks the first bump to the first pad and the second bump to the second pad. | 12-22-2011 |
Soon Lock Goh, Mutiara MY
| Patent application number | Description | Published |
|---|---|---|
| 20100129964 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH A BUMP USING A CARRIER - A method of manufacturing a semiconductor package with a bump using a carrier. One embodiment provides forming a bump on a carrier. A gap is formed in the carrier that undercuts the bump. A semiconductor chip is attached to the carrier. The chip is electrically connected to the bump. An encapsulant is deposited into the gap. The carrier is removed from the bump. | 05-27-2010 |
Soon Lock Goh, Malacca MY
| Patent application number | Description | Published |
|---|---|---|
| 20090093090 | METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE COMPRISING SURFACE-MOUNTABLE FLAT EXTERNAL CONTACTS - A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts. | 04-09-2009 |
Teck Joo Goh, Johor MY
| Patent application number | Description | Published |
|---|---|---|
| 20080300887 | Usage Model of Online/Offline License for Asset Control - It is disclosed a method that may monitor and control loan instalment or other fee payment for an asset. The method may comprise checking validity status of a first license that comprises allowable usage information of a user device; and disabling use of the user device based on the validity status to control payment for the user device. | 12-04-2008 |
| 20090044026 | Integrated uninterrupted power supply unit - A system may provide integrated uninterrupted power supply for computer systems. The system comprise a first unit that outputs an AC input voltage, and produces an AC output voltage from a battery voltage in response to the AC input voltage being absent; and a second unit that produces a DC output voltage from the AC input voltage, and produces the DC output voltage from the battery voltage in response to the AC input voltage being absent. | 02-12-2009 |
Toh Hau Goh, Melaka MY
| Patent application number | Description | Published |
|---|---|---|
| 20110220755 | AUTO-REEL CHANGER - A device for the automatic coiling and/or uncoiling on reels (28) of a flexible tape carrier of electronic components (60), the device comprising a coiling location (80) where a reel (28) can be connected to a rotation actuator, and retractable tape guides (35), consisting of articulated jaws (35) that can be closed together forming a channel to guide the flexible tape (60) and connect a free end of the flexible (60) tape (60) to a hub (29) of the reel (28), the device further having a stopper element (87) that engages with the slot in the reel hub, in order to stop the reel in a position in which the slot is aligned with the tape guide. | 09-15-2011 |
Yoke Chin Goh, Melaka MY
| Patent application number | Description | Published |
|---|---|---|
| 20110121461 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 05-26-2011 |
Yoke Chin Goh, Tangkak Johor MY
| Patent application number | Description | Published |
|---|---|---|
| 20090250807 | Electronic Component and Method for its Production - An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s). | 10-08-2009 |