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Goarin
Pierre Goarin, Graz AT
| Patent application number | Description | Published |
|---|---|---|
| 20100320513 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device ( | 12-23-2010 |
| 20110006352 | REVERSE ENGINEERING RESISTANT READ ONLY MEMORY - A read only memory is manufactured with a plurality of transistors ( | 01-13-2011 |
Pierre Goarin, Graz BE
| Patent application number | Description | Published |
|---|---|---|
| 20100096694 | PLANAR EXTENDED DRAIN TRANSISTOR AND METHOD OF PRODUCING THE SAME - A planar extended drain transistor ( | 04-22-2010 |
Pierre Goarin, Leuven BE
| Patent application number | Description | Published |
|---|---|---|
| 20090212347 | SONOS MEMORY DEVICE WITH OPTIMIZED SHALLOW TRENCH ISOLATION - Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising:—providing the substrate having the first semiconductor layer;—depositing the charge trapping layer;—depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and—creating a shallow trench isolation in between said at least two non-volatile memory cells. | 08-27-2009 |
Pierre Goarin, Etterbeek BE
| Patent application number | Description | Published |
|---|---|---|
| 20080203462 | Finfet-Based Non-Volatile Memory Device - A non-volatile memory device on a substrate layer ( | 08-28-2008 |
| 20080230824 | Double Gate Non-Volatile Memory Device and Method of Manufacturing - The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer. | 09-25-2008 |