Patent application number | Description | Published |
20110080189 | YIELD ENHANCEMENT FOR STACKED CHIPS THROUGH ROTATIONALLY-CONNECTING-INTERPOSER - A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield. | 04-07-2011 |
20110089495 | APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS - Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step. | 04-21-2011 |
20110115082 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 05-19-2011 |
20110180896 | METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS - A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided. | 07-28-2011 |
20120187502 | APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS - Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step. | 07-26-2012 |
20130005126 | APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS - Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step. | 01-03-2013 |
Patent application number | Description | Published |
20100240227 | ACTIVATING DOPANTS USING MULTIPLE CONSECUTIVE MILLISECOND-RANGE ANNEALS - A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds. | 09-23-2010 |
20120098067 | STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR - A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided. | 04-26-2012 |
20120126294 | WAFER FILL PATTERNS AND USES - A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements. | 05-24-2012 |
20120146682 | YIELD ENHANCEMENT FOR STACKED CHIPS THROUGH ROTATIONALLY-CONNECTING-INTERPOSER - A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield. | 06-14-2012 |
20120241977 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 09-27-2012 |
20130041494 | ALIGNMENT DATA BASED PROCESS CONTROL SYSTEM - Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step. | 02-14-2013 |
20130106455 | PRESSURE SENSING AND CONTROL FOR SEMICONDUCTOR WAFER PROBING | 05-02-2013 |
20130200482 | SHALLOW TRENCH ISOLATION FOR DEVICE INCLUDING DEEP TRENCH CAPACITORS - A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less. | 08-08-2013 |
20140145351 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 05-29-2014 |
Patent application number | Description | Published |
20080230840 | ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION - A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate. | 09-25-2008 |
20080233687 | ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION - A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate. | 09-25-2008 |
20080237720 | HIGH MOBILITY CMOS CIRCUITS - Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors. | 10-02-2008 |
20090101993 | HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE - The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å. | 04-23-2009 |