| Patent application number | Description | Published |
|---|
| 20090244074 | Apparatus, System, and Method For Using Page Table Entries in a Graphics System to Provide Storage Format Information For Address Translation - A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory. | 10-01-2009 |
| 20100106921 | SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS - A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss. | 04-29-2010 |
| 20100138614 | Compression Status Bit Cache And Backing Store - One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data. | 06-03-2010 |
| 20100146218 | System And Method For Maintaining Cache Coherency Across A Serial Interface Bus - A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. | 06-10-2010 |
| 20100153658 | Deadlock Avoidance By Marking CPU Traffic As Special - Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel | 06-17-2010 |
| 20110072177 | VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER - The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled. | 03-24-2011 |
| 20110087840 | EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CACHING - One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information. | 04-14-2011 |
