| Patent application number | Description | Published |
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| 20080211015 | METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE - A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers. | 09-04-2008 |
| 20080211021 | Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture - According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region. | 09-04-2008 |
| 20090321826 | METHOD FOR MANUFACTURING A HIGH INTEGRATION DENSITY POWER MOS DEVICE - A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide. | 12-31-2009 |
| 20100167481 | MANUFACTURING PROCESS OF A VERTICAL-CONDUCTION MISFET DEVICE WITH GATE DIELECTRIC STRUCTURE HAVING DIFFERENTIATED THICKNESS AND VERTICAL-CONDUCTION MISFET DEVICE THUS MANUFACTURE - According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region. | 07-01-2010 |
| Patent application number | Description | Published |
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| 20090090605 | TOUCH SWITCH FOR ELECTRICAL APPLIANCES AND ELECTRICAL APPLIANCE PROVIDED WITH SUCH SWITCH - A touch switch for an electrical appliance having a capacitive flat electrode, a light source, a transparent cover and a printed circuit board connected to the electrode is disclosed. The light source is mounted on a face of the printed circuit board opposite the transparent cover and the printed circuit board presents a cut-out for allowing light transmission from the light source towards the transparent cover. | 04-09-2009 |
| 20090090611 | CAPACITIVE TOUCH SWITCH AND DOMESTIC APPLIANCE PROVIDED WITH SUCH SWITCH - A capacitive touch switch having a printed circuit board and capacitive electrode provided on a surface of the printed circuit board is disclosed. The printed circuit board is interposed between a transparent planar light guide and the electrode, the planar light guide being attached to a first face of a transparent cover whose second face is adapted to be touched by the user, a light source being connected to the printed circuit board and being able to convey light to the planar light guide. | 04-09-2009 |
| 20090091906 | CAPACITIVE TOUCH SWITCH AND DOMESTIC APPLIANCE PROVIDED WITH SUCH SWITCH - A capacitive touch switch having a printed circuit board and a capacitive electrode connected to the circuit board is disclosed. The printed circuit board is transparent and is interposed between a planar light guide provided with a light source and a non-conductive transparent cover, the electrode being icon-shaped and supported by the printed circuit board. | 04-09-2009 |
| 20100155206 | TOUCH SWITCH FOR ELECTRICAL APPLIANCES AND ELECTRICAL APPLIANCE PROVIDED WITH SUCH SWITCH - A touch switch for an electrical appliance having a capacitive flat electrode, a light source, a transparent cover and a printed circuit board connected to the electrode is disclosed. The light source is mounted on a face of the printed circuit board opposite the transparent cover and the printed circuit board presents a cut-out for allowing light transmission from the light source towards the transparent cover. | 06-24-2010 |
