Patent application number | Description | Published |
20140091929 | Systems and Methods for Secure Alarmed Armored Protective Distribution Systems and Management - A fiber optic network has alarmed fiber optic lines in the cables connecting a secured junction box to plural user lock boxes. An outgoing alarm line and return alarm line in each cable connect the junction box to each user box. The outgoing alarm line is looped to the return alarm line inside the user lock box. The return alarm line is looped to the outgoing alarm line of a different cable inside the junction box to interconnect a plurality of alarm lines passing through a plurality of user boxes. A detector detects an alarm signal in the connected alarm lines to trigger an intrusion alarm. | 04-03-2014 |
20140153889 | Hardware and Methods for Secure Alarmed Armored Protective Distribution Systems and Management - A fiber optic network has alarmed fiber optic lines in the cables connecting a secured junction box to plural user lock boxes. An outgoing alarm line and return alarm line in each cable connect the junction box to each user box. The outgoing alarm line is looped to the return alarm line inside the user lock box. The return alarm line is looped to the outgoing alarm line of a different cable inside the junction box to interconnect a plurality of alarm lines passing through a plurality of user boxes. A detector detects an alarm signal in the connected alarm lines to trigger an intrusion alarm. Power to the components in the box is disconnected when the box is opened and ventilation openings to the box are closed when the box is closed. | 06-05-2014 |
20140230553 | Method of Detecting Movement Using a Metallic Conductors - A method for monitoring movement of an element such as a cable is carried out by providing a pair of conductive elements each extending along an extent of the cable or other element to be monitored. A DC potential difference is applied between the conductive elements. The conductive elements are provided with an intervening material therebetween, which can be a continuous dielectric or can be other insulating material which varies in spacing and capacitance value along its length, such that the movement causes a change in capacitive coupling between the conductive elements at points or areas where the movement occurs so as to generate a changing voltage therebetween. The changing voltage as an amplified and filtered variable electrical signal is analyzed for monitoring the changing voltage for perturbations caused by the movement of the element. | 08-21-2014 |
20150015398 | Alarm System for a Single Mode Optical Fiber Network - A method is provided for detecting intrusion into an optical cable of a single mode optical fiber network comprising where monitoring light signals are transmitted along a telecommunications optical fiber to be monitored either along a fiber additional to a data fiber or by multiplexing onto a common fiber. The received monitoring light signals after transmission along the telecommunications optical fiber are analyzed for changes indicative of movement of the optical fiber for detecting an intrusion event. The monitoring light signals at the receive end of the fiber signals are monitored by feeding the signals from the single mode fiber into a multi-mode fiber in a manner which causes changes in modal power distribution which can be detected by taking a portion only of the modes. | 01-15-2015 |
20150333822 | Network Alarm System Utilizing a Single Sensing Fiber - A method is provided for detecting intrusion into an optical cable of an optical network comprising where monitoring light signals are transmitted along a telecommunications optical fiber to be monitored either along a fiber additional to a data fiber or by multiplexing onto a common fiber. The received monitoring light signals after transmission along the telecommunications optical fiber are analyzed for changes indicative of movement of the optical fiber for detecting an intrusion event. The monitoring light signals at the receive end of the fiber signals are returned along the same fiber by a coupler where the legs are connected or by a reflective material. | 11-19-2015 |
Patent application number | Description | Published |
20090003840 | Controlling a bias voltage for a Mach-Zehnder modulator - In one embodiment, the present invention includes a controller coupled to an optical modulator to receive a dither signal, determine a difference between the dither signal and a previous dither signal, determine a derivative of the difference with respect to a bias voltage difference between first and second bias voltages, and control a bias voltage for the optical modulator based on the derivative. Other embodiments are described and claimed. | 01-01-2009 |
20130290766 | Methods and Systems for Recovering Intermittent Timing-Reference Signals - A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble. | 10-31-2013 |
20130346721 | MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES - A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied. | 12-26-2013 |
Patent application number | Description | Published |
20090161453 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship. | 06-25-2009 |
20110216611 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 09-08-2011 |
20120023363 | PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL - Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device. | 01-26-2012 |
20130086449 | Sharing a Check Bit Memory Device Between Groups of Memory Devices - A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer. | 04-04-2013 |
20150243343 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 08-27-2015 |
20150248926 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 09-03-2015 |
20150255144 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 09-10-2015 |
20150331732 | MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNT - An integrated circuit memory device is disclosed. The memory device includes at least one group of storage cells. Logic derives a count of error code correction events for each of the at least one group of storage cells. Storage stores the count. A memory control interface selectively communicates the count to a memory controller. | 11-19-2015 |
20160125930 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 05-05-2016 |