Patent application number | Description | Published |
20080205155 | Systems and methods to reduce interference between memory cells - Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page of a second group of memory cells to hold a second least significant bit. Once the lower page is programmed, the voltage may be shifted to the upper page of each memory cell into a final range representing one or more most significant bits to be programmed. Each memory cell may store a voltage within a final programmed range representing a binary value. | 08-28-2008 |
20080239806 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 10-02-2008 |
20080285341 | READING NON-VOLATILE MULTILEVEL MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition. | 11-20-2008 |
20090080253 | DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY - Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed. | 03-26-2009 |
20100097856 | FLASH MEMORY AND ASSOCIATED METHODS - In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period. | 04-22-2010 |
20100128534 | Word Line Voltage Boost System and Method for Non-Volatile Memory Devices and Memory Devices and Processor-Based System Using Same - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 05-27-2010 |
20100135075 | READING NON-VOLATILE MULTILEVEL MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition. | 06-03-2010 |
20100165739 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 07-01-2010 |
20110134701 | MEMORY KINK COMPENSATION - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 06-09-2011 |
20110157980 | TECHNIQUE TO REDUCE FG-FG INTERFERENCE IN MULTI BIT NAND FLASH MEMORY IN CASE OF ADJACENT PAGES NOT FULLY PROGRAMMED - A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed. | 06-30-2011 |
20110170359 | WORD LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 07-14-2011 |
20110280082 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 11-17-2011 |
20110299333 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described. | 12-08-2011 |
20120081972 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY - Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory. | 04-05-2012 |
20120127794 | PROGRAM VERIFY OPERATION IN A MEMORY DEVICE - Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse. | 05-24-2012 |
20120224429 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS | 09-06-2012 |
20120243318 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described. | 09-27-2012 |
20120262993 | SENSING SCHEME IN A MEMORY DEVICE - Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current. | 10-18-2012 |
20120307564 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 12-06-2012 |
20130028022 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb. | 01-31-2013 |
20130039138 | METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES - Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after the data has been loaded into a buffer. The direction of the mapping is determined by the operation (e.g., programming or reading). | 02-14-2013 |
20130188427 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 07-25-2013 |
20130201764 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described. | 08-08-2013 |
20130286743 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 10-31-2013 |
20130343132 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY - Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory. | 12-26-2013 |
20140043912 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 02-13-2014 |
20140133224 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 05-15-2014 |
20140204674 | LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 07-24-2014 |
20140219032 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation. | 08-07-2014 |
20150049556 | PROGRAM VERIFY OPERATION IN A MEMORY DEVICE - Methods for program verifying a memory cell include generating an access line voltage in response to a count and applying the access line voltage to a control gate of the memory cell, and generating a pass signal in response to the access line voltage activating the memory cell. Methods further include comparing at least a portion of the count to an indication of a desired threshold voltage of the memory cell, and when the at least a portion of the count matches the indication of the desired threshold voltage of the memory cell, determining if the pass signal is present. Methods further include generating a signal indicative of a desire to inhibit further programming of the memory cell if the pass signal is present when the match is indicated. | 02-19-2015 |
20150063031 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window. | 03-05-2015 |
20150085581 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described. | 03-26-2015 |