| Patent application number | Description | Published |
|---|
| 20080206945 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 08-28-2008 |
| 20080211009 | Process for manufacturing an electronic device integrated on semiconductor substrate comprising non volatile floating gate memories and an associated circuitry and corresponding electronic device - An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing:
| 09-04-2008 |
| 20080266929 | REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY - A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells. | 10-30-2008 |
| 20100047980 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 02-25-2010 |
| 20100308296 | PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER - A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness. | 12-09-2010 |
| 20110248382 | DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION - A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars. | 10-13-2011 |
| Patent application number | Description | Published |
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| 20100155894 | Fabricating Bipolar Junction Select Transistors For Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 06-24-2010 |
| 20100221904 | Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device - A non-volatile memory electronic device integrated on a semiconductor substrate includes non-volatile memory cells organized in a matrix, and circuitry associated therewith. Each memory cell includes a gate electrode projecting from the semiconductor substrate. Source and drain regions are formed in the semiconductor substrate and aligned with the gate electrodes. At least one portion of the gate electrodes are insulated from each other by air-gaps which are closed on top by a third non-conforming dielectric layer. | 09-02-2010 |
| 20110312153 | METHOD OF MAKING A FLOATING GATE NON-VOLATILE MOS SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED CAPACITIVE COUPLING AND DEVICE THUS OBTAINED - A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed. | 12-22-2011 |
