| Patent application number | Description | Published |
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| 20080216085 | System and Method for Virtual Adapter Resource Allocation - A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis. | 09-04-2008 |
| 20080307147 | COMPUTER SYSTEM BUS BRIDGE - A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module. | 12-11-2008 |
| 20090007118 | Native Virtualization on a Partially Trusted Adapter Using PCI Host Bus, Device, and Function Number for Identification - A mechanism that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to perform I/O transactions using the PCI host bus, device, and function numbers to validate that an I/O transaction originated from the proper host is provided. Additionally, a method for facilitating identification of a transaction source partition is provided. An input/output transaction that is directed to a physical adapter is originated from a system image of a plurality of system images. The host data processing system adds an identifier of the system image to the input/output transaction. The input/output transaction is then conveyed to the physical adapter for processing of the input/output transaction. | 01-01-2009 |
| 20090144462 | Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request - A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation. | 06-04-2009 |
| 20090271802 | APPLICATION AND VERB RESOURCE MANAGEMENT - A computer program product is provided. The product including a computer readable storage medium including computer readable program code for controlling access to computer memory. the computer readable program code including first instructions for communicating work queue elements with an application layer and with a verb layer, wherein the application layer and the verb layer each may request a completion notification to determine whether a work queue elements with an application layer and with a verb layer, wherein the application layer and the verb layer each may request a completion notification to determine whether a work queue element has been completed, and second instructions for indicating completion of the work queue elemens in response to the layer requesting completion notification, wherein both the application layer and the verb layer are capable of checking if at least one of the work queue elements is completed, independently of each other, such that the application layer does not interface with the verb layer to determine completion status of the work queue elements; wherein communicating work queue elements includes communicating a consumer work request comprising an application request bit, adapted to indicate an application request for completion notification, and a verb request bit, adapted to indicate a verb request for completion notification; wherein if the application request bit is set, then a completion queue element is provided that indicates completion of the communicated consumer work request and if the verb request bit is set, then a status field of the communicated work queue element is updated to indicate completion of the communicated work queue element; wherein the application layer queries the completion queue element to find out if the communicated consumer work request is completed and the verb layer queries the status field of the communicated work queue element to find out if the communicated work queue element is completed, and wherein the work queue elements are stored in a work queue and the completion queue elements are stored in a completion queue such that the work queue and the completion queue elements are located in different address spaces, each independently accessible to the application layer and the verb layer. | 10-29-2009 |
| 20100013678 | METHOD AND APPARATUS FOR DATA DECOMPRESSION IN THE PRESENCE OF MEMORY HIERARCHIES - A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that the first data is located in the remote memory, stalling the first decompression copy operation, performing a second decompression operation using second data that is located in the history buffer on the local memory and fetching the first data from the remote memory to the history buffer on the local memory. The method further includes performing the first decompression operation using the first data in the history buffer on the local memory. | 01-21-2010 |
| 20100180060 | Managing Message Signaled Interrupts - Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed. | 07-15-2010 |
| 20100253556 | METHOD OF CONSTRUCTING AN APPROXIMATED DYNAMIC HUFFMAN TABLE FOR USE IN DATA COMPRESSION - A novel and useful method of constructing a fast approximation of a dynamic Huffman table from a data sample comprising a subset of data to be compressed. The frequency of incidence of each symbol in the sample is calculated, and the symbols are then allocated to predefined bins based on their frequency of incidence. The bins are then transformed into binary sub-trees, where the leaf nodes of the binary sub-trees comprise the symbols of the bin associated with the binary sub-trees. The binary sub-trees are then combined via nesting, thereby creating a coarse grained binary tree, where all leaves are mapped to a specified number of depths. The coarse grained binary tree is then traversed, thereby yielding a canonical code for each symbol, thereby defining the entries for a dynamic Huffman table. | 10-07-2010 |
| 20110071990 | Fast History Based Compression in a Pipelined Architecture - A novel and useful system and method of fast history compression in a pipelined architecture with both speculation and low-penalty misprediction recovery. The method of the present invention speculates that a current input byte does not continue an earlier string, but either starts a new string or represents a literal (no match). As previous bytes are checked if they start a string, the method of the present invention detects if speculation for the current byte is correct. If speculation is not correct, then various methods of recovery are employed, depending on the repeating string length. | 03-24-2011 |
