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Giles, OR
Andrew Joseph Giles, Newport, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100090866 | Optical Distress Beacon For Use In Space Environments - A beacon system includes emitter devices, driver circuitry configured for controlling the emitter devices, and at least one processor programmed to receive and process one or more inputs and control the driver circuitry to actuate the emitter devices. In an example embodiment, the emitter devices include visible light sources that are oriented to provide omni-directional visibility for the beacon system. In an example embodiment, components of the beacon system including the emitter devices, driver circuitry and at least one processor are configured such that in a space environment heat generated by the beacon system is dissipated sufficiently well to prevent the beacon system from overheating. | 04-15-2010 |
Chris Giles, Sherwood, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20110222670 | ALERTING SYSTEM AND A METHOD OF ALERTING DESIGNATED PARTIES - An alerting system is disclosed including in one embodiment: (1) a detection system configured to identify an initiated emergency call, identify a calling device initiating the emergency call and generate a detection message that identifies the calling device, the detection system implemented at central office equipment of a telephone company, (2) a determining system configured to receive the detection message, confirm if the calling device is registered with an alerting service and generate a confirmation message when the calling device is registered, the determining system configured to uniquely correspond with the telephone company and (3) a notification system configured to receive the confirmation message, determine parties associated with the calling device and contact the parties with a notification message, the notification message limited to information obtained concurrent with or before occurrence of the emergency call, the determining system and the notification system independent of the telephone company. | 09-15-2011 |
Martin Giles, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090315114 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 12-24-2009 |
| 20090315120 | RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS - An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via. | 12-24-2009 |
| 20100025775 | Replacement spacers for mosfet fringe capacatance reduction and processes of making same - A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact. | 02-04-2010 |
Martin D. Giles, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090032872 | MULTIPLE OXIDE THICKNESS FOR A SEMICONDUCTOR DEVICE - Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin. | 02-05-2009 |
| 20090075445 | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress - A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si | 03-19-2009 |
| 20090096025 | Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer - Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed. | 04-16-2009 |
| 20090152589 | Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors - A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies. | 06-18-2009 |
| 20110147847 | Methods and apparatus to reduce layout based strain variations in non-planar transistor structures - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies. | 06-23-2011 |