| Patent application number | Description | Published |
|---|
| 20110148901 | Method and System For Tile Mode Renderer With Coordinate Shader - A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader. | 06-23-2011 |
| 20110216069 | Method And System For Compressing Tile Lists Used For 3D Rendering - A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices. | 09-08-2011 |
| 20110221743 | Method And System For Controlling A 3D Processor Using A Control List In Memory - A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device. | 09-15-2011 |
| 20110227920 | Method and System For a Shader Processor With Closely-Coupled Peripherals - A method and system are provided in which a first instruction associated with a graphics rendering operation may be executed in a shader processor, the shader processor may receive result information associated with an intermediate portion of the graphics rendering operation performed by a peripheral device operably coupled to a register file bus in the shader processor, and the shader processor may execute a second instruction associated with the graphics rendering operation based on the received result information. The register file bus may be utilized for handling execution of intermediate instructions associated with the intermediate portion of the graphics rendering operation. The peripheral device may be accessed via one or more register file addresses associated with the peripheral device. The peripheral device may be operably coupled to the shader processor via a FIFO. | 09-22-2011 |
| 20110242113 | Method And System For Processing Pixels Utilizing Scoreboarding - In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete. | 10-06-2011 |
| Patent application number | Description | Published |
|---|
| 20090023249 | Wire bonded wafer level cavity package - A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them. | 01-22-2009 |
| 20090065907 | Semiconductor packaging process using through silicon vias - A microelectronic unit | 03-12-2009 |
| 20100230795 | STACKED MICROELECTRONIC ASSEMBLIES HAVING VIAS EXTENDING THROUGH BOND PADS - A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements. Each of the first and second microelectronic elements can include a conductive layer extending along a face of such microelectronic element. At least one of the first and second microelectronic elements can include a recess extending from the rear surface towards the front surface, and a conductive via extending from the recess through the bond pad and electrically connected to the bond pad, with a conductive layer connected to the via and extending along a rear face of the microelectronic element towards an edge of the microelectronic element. A plurality of leads can extend from the conductive layers of the first and second microelectronic elements and a plurality of terminals of the assembly can be electrically connected with the leads. | 09-16-2010 |
| 20100242269 | COMPACT LENS TURRET ASSEMBLY - An electronic camera module incorporates a sensor unit ( | 09-30-2010 |
| 20100270679 | MICROELECTRONIC PACKAGES FABRICATED AT THE WAFER LEVEL AND METHODS THEREFOR - A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer. | 10-28-2010 |
| 20110006432 | RECONSTITUTED WAFER STACK PACKAGING WITH AFTER-APPLIED PAD EXTENSIONS - A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements ( | 01-13-2011 |
| 20110248410 | STACK PACKAGES USING RECONSTITUTED WAFERS - A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads. | 10-13-2011 |
