| Patent application number | Description | Published |
| 20090129377 | SERVICE FOR MAPPING IP ADDRESSES TO USER SEGMENTS - A system is disclosed that uses behavioral data collected by ISPs to categorize particular ISP subscribers. The behavioral data may, for example, include the identities of particular web sites and/or web pages accessed by particular subscribers, the search queries used by the subscribers to conduct Internet searches, and/or other types of behavioral information. The ISP subscribers are assigned to particular behavioral categories or “segments” using a behavioral segmentation schema that maps particular subscriber behaviors to particular behavioral segments. The ISP subscribers may also be mapped to other segment types, such as demographic segments derived from off-line data about the subscribers. The subscriber-to-segment mappings are made available to content targeting entities via a query interface that, for example, supports queries of the form “what are the segments associated with IP address X?” | 05-21-2009 |
| 20090132559 | BEHAVIORAL SEGMENTATION USING ISP-COLLECTED BEHAVIORAL DATA - A system is disclosed that uses behavioral data collected by ISPs to categorize particular ISP subscribers. The behavioral data may, for example, include the identities of particular web sites and/or web pages accessed by particular subscribers, the search queries used by the subscribers to conduct Internet searches, and/or other types of behavioral information. The ISP subscribers are assigned to particular behavioral categories or “segments” using a behavioral segmentation schema that maps particular subscriber behaviors to particular behavioral segments. The ISP subscribers may also be mapped to other segment types, such as demographic segments derived from off-line data about the subscribers. The subscriber-to-segment mappings are made available to content targeting entities via a query interface that, for example, supports queries of the form “what are the segments associated with IP address X?” | 05-21-2009 |
| 20110289190 | SERVICE FOR ASSOCIATING IP ADDRESSES WITH USER SEGMENTS - A system is disclosed that maps IP addresses and geographic regions to particular categories or “segments” reflective of user profiles. The mappings may be based on behavioral data reflective of user browsing activities, offline data (e.g., survey data or demographic data), or a combination thereof. In one embodiment, the mappings are generated using data collected by a plurality of Internet Service Providers (ISPs) regarding their subscribers. The system also includes a query interface that enables content providers to retrieve segment data associated with particular IP addresses. | 11-24-2011 |
| Patent application number | Description | Published |
| 20080197383 | METHOD OF MANUFACTURING A SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT - A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using the dislocations in the dislocation region. Vacancies are formed in the second layer. Second interstitials in the second layer are at least partially eliminated using the vacancies in the second layer. | 08-21-2008 |
| 20080203484 | FIELD EFFECT TRANSISTOR ARRANGEMENT AND METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT - A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation; a second layer formed above at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation; a first buried oxide layer formed between the first layer and the substrate; a second buried oxide layer formed between the second layer and the substrate; a first field effect transistor formed in or on the first layer, the first field effect transistor having a first conductivity type; and a second field effect transistor formed in or on the second layer, the second field effect transistor having a second conductivity type different from the first conductivity type. | 08-28-2008 |
| 20080286908 | Method of Producing a Semiconductor Element in a Substrate - A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms. | 11-20-2008 |
| 20090085035 | Method of Producing a Semiconductor Element in a Substrate and a Semiconductor Element - A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms. | 04-02-2009 |
| 20100041185 | METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT - A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer. | 02-18-2010 |
| 20100127262 | Semiconductor Element - A semiconductor element including a substrate and at least one shallow junction formed in the substrate wherein doping atoms are disposed in the shallow junction. A plurality of carbide precipitates and micro-cavities is disposed in the substrate below the at least one shallow junction. | 05-27-2010 |
| Patent application number | Description | Published |
| 20080290425 | Method for Fabricating a Semiconductor Element, and Semiconductor Element - In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms. | 11-27-2008 |
| 20090085110 | SEMICONDUCTOR DEVICE EMPLOYING PRECIPITATES FOR INCREASED CHANNEL STRESS - A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region. | 04-02-2009 |