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Gilday
David Michael Gilday, Chatteris GB
| Patent application number | Description | Published |
|---|---|---|
| 20100138640 | Reset synchronisation - Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal. | 06-03-2010 |
| 20100241777 | Power efficient interrupt detection - Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry. | 09-23-2010 |
David Michael Gilday, Cambridgeshire GB
| Patent application number | Description | Published |
|---|---|---|
| 20090222649 | Initialisation of a pipelined processor - A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction. | 09-03-2009 |
David Michael Gilday, Cambridge GB
| Patent application number | Description | Published |
|---|---|---|
| 20090094439 | Data processing apparatus and method employing multiple register sets - A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus. | 04-09-2009 |
John Peter Gilday, Bristol GB
| Patent application number | Description | Published |
|---|---|---|
| 20100137304 | NOVEL CRYSTALLINE FORMS OF THE ANTI-CANCER COMPOUND ZD1839 - The invention concerns certain crystalline solvates and hydrates of the compound of the Formula I | 06-03-2010 |