| Patent application number | Description | Published |
|---|
| 20080277739 | Finfet Transistors - A fin FET array includes a number of fins | 11-13-2008 |
| 20090289298 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 11-26-2009 |
| 20100025766 | TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SUCH A TRANSISTOR DEVICE - A transistor device ( | 02-04-2010 |
| 20100044760 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 02-25-2010 |
| 20100066348 | APPARATUS AND METHOD FOR MOLECULE DETECTION USING NANOPORES - A detector device comprises a substrate ( | 03-18-2010 |
| 20100097135 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel transistor includes source diffusion ( | 04-22-2010 |
| 20110018065 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier ( | 01-27-2011 |
