Patent application number | Description | Published |
20080277739 | Finfet Transistors - A fin FET array includes a number of fins | 11-13-2008 |
20090289298 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 11-26-2009 |
20100025766 | TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SUCH A TRANSISTOR DEVICE - A transistor device ( | 02-04-2010 |
20100044760 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 02-25-2010 |
20100066348 | APPARATUS AND METHOD FOR MOLECULE DETECTION USING NANOPORES - A detector device comprises a substrate ( | 03-18-2010 |
20100097135 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel transistor includes source diffusion ( | 04-22-2010 |
20110018065 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier ( | 01-27-2011 |
20110208457 | ELECTROCHEMICAL POTENTIOMETRIC SENSING WITHOUT REFERENCE ELECTRODE - The invention relates to a method of determining a charged particle concentration in an analyte ( | 08-25-2011 |
20110241103 | METHOD OF MANUFACTURING A TUNNEL TRANSISTOR AND IC COMPRISING THE SAME - A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate ( | 10-06-2011 |
20110241767 | CHARGE-PUMP CIRCUIT - The invention describes a charge-pump circuit ( | 10-06-2011 |
20110291806 | FOOD PACKAGE WITH INTEGRATED RFID-TAG AND SENSOR - A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer. | 12-01-2011 |
20120086058 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source. | 04-12-2012 |
20120154019 | FIELD-EFFECT MAGNETIC SENSOR - A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals. | 06-21-2012 |
Patent application number | Description | Published |
20120280278 | Normally-Off High Electron Mobility Transistors - A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage. | 11-08-2012 |
20130043484 | HEMT WITH INTEGRATED LOW FORWARD BIAS DIODE - A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions. | 02-21-2013 |
20130153919 | III-V Semiconductor Devices with Buried Contacts - A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate. | 06-20-2013 |
20130153967 | Compound Semiconductor Device with Buried Field Plate - A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material. | 06-20-2013 |
20130221366 | NORMALLY-OFF COMPOUND SEMICONDUCTOR TUNNEL TRANSISTOR - Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher. | 08-29-2013 |
20130256699 | Gate Overvoltage Protection for Compound Semiconductor Transistors - A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material. | 10-03-2013 |
20130320350 | Compound Semiconductor Transistor with Self Aligned Gate - A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer. | 12-05-2013 |
20140034962 | Normally-Off Compound Semiconductor Tunnel Transistor with a Plurality of Charge Carrier Gases - A tunnel transistor includes a first compound semiconductor, a second compound semiconductor on the first compound semiconductor, and a third compound semiconductor on the second compound semiconductor. A source extends through the second compound semiconductor into the first compound semiconductor. A drain spaced apart from the source extends through the third compound semiconductor into the second compound semiconductor. A first two-dimensional charge carrier gas extends in the first compound semiconductor from the source toward the drain and ends prior to reaching the drain. A second two-dimensional charge carrier gas extends in the second compound semiconductor from the drain toward the source and ends prior to reaching the source. A gate is over the first and second two-dimensional charge carrier gases. A corresponding method of manufacturing the tunnel transistor is also provided. | 02-06-2014 |
20140103398 | RF POWER HEMT GROWN ON A SILICON OR SIC SUBSTRATE WITH A FRONT-SIDE PLUG CONNECTION - A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source. | 04-17-2014 |
20140106516 | SELF-DOPED OHMIC CONTACTS FOR COMPOUND SEMICONDUCTOR DEVICES - A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers. | 04-17-2014 |
20140124791 | HEMT with Compensation Structure - A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the first III-V semiconductor region. The high electron mobility transistor further includes a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second III-V semiconductor regions are spaced apart from one another by the compensation structure. The compensation structure has a different band gap than the first and second III-V semiconductor regions. | 05-08-2014 |
20140374765 | Gate Stack for Normally-Off Compound Semiconductor Transistor - A normally-off compound semiconductor transistor includes a heterostructure body and a gate stack on the heterostructure body. The heterostructure body includes a source, a drain spaced apart from the source, and a channel for connecting the source and the drain. The channel includes a first two-dimensional charge carrier gas of a first polarity arising in the heterostructure body due to piezoelectric effects. The gate stack controls the channel in a region of the heterostructure body under the gate stack. The gate stack includes at least one III-nitride material which gives rise to a second two-dimensional charge carrier gas of a second polarity opposite the first polarity in the gate stack or in the heterostructure body under the gate stack due to piezoelectric effects. The second two-dimensional charge carrier gas counter-balances polarization charges in the first two-dimensional charge carrier gas so that the channel is disrupted under the gate stack. | 12-25-2014 |