| Patent application number | Description | Published |
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| 20080244571 | VIRTUAL INTERRUPT PROCESSING IN A LAYERED VIRTUALIZATION ARCHITECTURE - Embodiments of apparatuses, methods, and systems for processing virtual interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to transfer control of the apparatus from a host to a guest. The recognition logic is to recognize a virtual interrupt request. The evaluation logic is to determine whether to transfer control from the guest to an intervening monitor in response to the virtual interrupt request. | 10-02-2008 |
| 20090007103 | INJECTING VIRTUALIZATION EVENTS IN A LAYERED VIRTUALIZATION ARCHITECTURE - Embodiments of apparatuses, methods, and systems for injecting virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to initiate a transfer of control of the apparatus from a host to a guest running on a virtual machine. The recognition logic is to recognize a request from the host to inject a virtualization event into the virtual machine. The evaluation logic is to identify an intervening monitor to handle the virtualization event. | 01-01-2009 |
| 20090077361 | DETECTING SPIN LOOPS IN A VIRTUAL MACHINE ENVIRONMENT - Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop | 03-19-2009 |
| 20090193222 | Maintaining Processor Resources During Architectural Events - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 07-30-2009 |
| 20090248951 | Maintaining Processor Resources During Architectural Events - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 10-01-2009 |
| 20090265709 | METHOD AND APPARATUS FOR FACILITATING RECOGNITION OF AN OPEN EVENT WINDOW DURING OPERATION OF GUEST SOFTWARE IN A VIRTUAL MACHINE ENVIRONMENT - In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open. | 10-22-2009 |
| 20100011186 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-14-2010 |
| 20100011187 | Performance enhancement of address translation using translation tables covering large address spaces - An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators. | 01-14-2010 |
| 20100100648 | ADDRESS WINDOW SUPPORT FOR DIRECT MEMORY ACCESS TRANSLATION - A apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations. | 04-22-2010 |
| 20110078389 | MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS - A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers. | 03-31-2011 |
| 20110087822 | VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM - A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine. | 04-14-2011 |
| 20110125952 | MAINTAINING PROCESSOR RESOURCES DURING ARCHITECTURAL EVENTS - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 05-26-2011 |
| 20110153983 | Gathering and Scattering Multiple Data Elements - According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception. | 06-23-2011 |
| 20110161541 | POSTING INTERRUPTS TO VIRTUAL PROCESSORS - Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure. | 06-30-2011 |
